DS21354LB Maxim Integrated Products, DS21354LB Datasheet - Page 101

• Manufacturer Part Number: DS21354LB
• Description: Network Controller & Processor ICs E1 Single-Chip Trans ceiver (SCT) E1 Fram
• Manufacturer: Maxim Integrated Products

Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK
RCHBLK
RMSYNC
RCHCLK
RSYNC
RCHBLK
RSYNC
RSYSCLK
RMSYNC
RCHCLK
RSER
RSYNC
RSYNC
RSIG
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1
NOTE 2: RSYNC IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 3: RSYNC IN THE INPUT MODE (RCR1.5 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
RSER
2
1
3
3
1
4
2
LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED
TO ON1).
CHANNEL 31
CHANNEL 23/31
A
CHANNEL 31
B
C
LSB
LSB MSB
D
MSB
101 of 124
CHANNEL 24/32
CHANNEL 32
A
CHANNEL 32
B
C
LSB
LSB MSB
D
F
MSB
CHANNEL 1
CHANNEL 1/2
CHANNEL 1
Note 4