CS8900A-CQZR Cirrus Logic Inc, CS8900A-CQZR Datasheet - Page 82

• Manufacturer Part Number: CS8900A-CQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

mine how frames will be transferred to host
memory, as described in Table 23.
5.2.3 Receive Frame Pre-Processing
The CS8900A pre-processes all receive
frames using a four step process:
1) Destination Address filtering;
82
Bit
Bit
Bit
A
B
D
7
F
A
B
B
D
Table 22. Registers 3 and B Interrupt Configuration
7
9
MissOvfloiE When set, there is an interrupt if
Table 23. Receive Frame Pre-Processing
Bit Name
RxDMAiE When set, there is an interrupt if
RxMissiE
RxDestiE
AutoRX DMAE When set, Auto-Switch DMA
Rx128iE
RxDMAonly
RxDMAsize
BufferCRC
DMABurst
Bit Name
Bit Name
StreamE
Register 17, BusCTL
Register B, BufCFG
Register 3, RxCFG
one or more frames are trans-
ferred via DMA.
When set, there is an interrupt if a
frame is missed due to insufficient
receive buffer space.
When set, there is an interrupt
after the first 128 bytes of receive
data have been buffered.
the RxMISS counter overflows.
When set, there is an interrupt
after the DA of an incoming frame
has been buffered.
When set, Stream Transfer
enabled.
When set, DMA slave opera-
tion used for all receive
frames.
enabled.
When set, the received CRC
is buffered.
When set, DMA operations
hold the bus for up to approx-
imately 28 µs. When clear,
DMA operations are continu-
ous.
When set, DMA buffer size is
64 Kbytes. When clear, DMA
buffer size is 16 Kbytes.
Operation
Operation
Operation
CIRRUS LOGIC PRODUCT DATASHEET
2) Early Interrupt Generation;
3) Acceptance filtering; and,
4) Normal Interrupt Generation.
Figure 21 provides a diagram of frame pre-
processing.
5.2.3.1 Destination Address Filtering
All incoming frames are passed through the
Destination Address filter (DA filter). If the
frame's DA passes the DA filter, the frame is
passed on for further pre-processing. If it fails
the DA filter, the frame is discarded. See
Section 5.2.10 on page 87 for a more detailed
description of DA filtering.
5.2.3.2 Early Interrupt Generation
The CS8900A support the following two early
interrupts that can be used to inform the host
that a frame is being received:
•
•
RxDest: The RxDest bit (Register C, BufE-
vent, Bit F) is set as soon as the Destina-
tion Address (DA) of the incoming frame
passes the DA filter. If the RxDestiE bit
(Register B, BufCFG, bit F) is set, the
CS8900A generates a corresponding inter-
rupt. Once RxDest is set, the host is al-
lowed to read the incoming frame's DA (the
first 6 bytes of the frame).
Rx128: The Rx128 bit (Register C, BufE-
vent, Bit B) is set as soon as the first 128
bytes of the incoming frame have been re-
ceived. If the Rx128iE bit (Register B, Buf-
CFG, bit B) is set, the CS8900A generates
a corresponding interrupt. Once the Rx128
bit is set, the RxDest bit is cleared and the
host is allowed to read the first 128 bytes of
the incoming frame. The Rx128 bit is
cleared by the host reading the BufEvent
register (either directly or through the Inter-
rupt Status Queue) or by the CS8900A de-
Crystal LAN™ Ethernet Controller
CS8900A
DS271F5