CS8900A-CQZR Cirrus Logic Inc, CS8900A-CQZR Datasheet - Page 42

• Manufacturer Part Number: CS8900A-CQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

to and from the host. The host simply writes to
and reads from these locations and internal
buffer memory is dynamically allocated be-
tween transmit and receive as needed. This
provides more efficient use of buffer memory
and better overall network performance. As a
result of this dynamic allocation, only one re-
ceive frame (starting at PacketPage base +
Notes: 1. All registers are accessed as words only.
Bus Interface Registers
Status and Control Registers
PacketPage
42
Address
002Ch
002Ah
0000h
0004h
0020h
0022h
0024h
0026h
0028h
0030h
0034h
0038h
0040h
0042h
0044h
0050h
0052h
2. Read operation from the reserved location provides undefined data. Writing to a reserved location or
undefined bits may result in unpredictable operation of the CS8900A.
Bytes
# of
174
28
12
4
2
2
2
2
2
2
4
4
4
8
2
2
2
Read/Write I/O Base Address
Read/Write Interrupt Number (0,1,2,or 3)
Read/Write DMA Channel Number (0, 1, or 2)
Read/Write Memory Base Address Register
Read/Write Boot PROM Base Address
Read/Write Boot PROM Address Mask
Read/Write EEPROM Command
Read/Write EEPROM Data
Read-only Product Identification Code
Read-only DMA Start of Frame
Read-only DMA Frame Count (12 Bits)
Read-only RxDMA Byte Count
Read only Received Frame Byte Counter
Type
-
-
-
-
Reserved
(20 Bit)
Reserved
Reserved
Reserved
Table 13. PacketPage Memory Address Map
CIRRUS LOGIC PRODUCT DATASHEET
Description
0400h) and one transmit frame (starting at
PacketPage base + 0A00h) are directly acces-
sible. See Section 4.7 on page 72.
4.2 PacketPage Memory Map
Table 13 shows the CS8900A PacketPage
memory address map: s
Section 4.3 on page 44
Note 2
Section 4.3 on page 44,
Section 4.7 on page 72
Section 3.2 on page 18,
Section 4.3 on page 44
Section 3.2 on page 18,
Section 4.3 on page 44
Section 4.3 on page 44,
Section 5.3 on page 90
Sections Section 4.3 on page 44,
”Receive DMA”
Section 4.3 on page 44,
Section 5.3 on page 90
Section 4.3 on page 44,
Section 4.9 on page 73
Section 3.6 on page 26,
Section 4.3 on page 44
Section 3.6 on page 26,
Section 4.3 on page 44
Note 2
Section 3.5 on page 25,
Section 4.3 on page 44
Section 3.5 on page 25,
Section 4.3 on page 44
Note 2
Section 4.3 on page 44,
Section 5.2.9 on page 86
Note 2
Crystal LAN™ Ethernet Controller
Cross Reference
CS8900A
DS271F5