DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 42

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DS3112N+W

Manufacturer Part Number
DS3112N+W
Description
Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3112N+W

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
150 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 4-5. HDLC Status Bit Flow
Transmit
Packet End
Signal from
HDLC
Internal Transmit
Low Water Mark
Signal from
HDLC
Internal Receive
High Water Mark
Signal from
HDLC
Internal Receive
Packet Start
Signal from
HDLC
Internal Receive
Packet End
Signal from
HDLC
Internal Transmit
FIFO Underrun
Signal from
HDLC
Internal Receive
FIFO Overrun
Signal from
HDLC
Internal Receive
Abort Detect
Signal from
HDLC
NOTE: ALL EVENT LATCHES ABOVE ARE CLEARED WHEN THE HSR REGISTER IS READ.
Event Latch
Event Latch
Event Latch
Event Latch
Event Latch
Event Latch
ROVR (IHSR Bit 13)
RHWM (IHSR Bit 4)
RABT (IHSR Bit 15)
TLWM (IHSR Bit 2)
TEND (IHSR Bit 0)
TUDR (IHSR Bit 3)
RPE (IHSR Bit 6)
RPS (IHSR Bit 5)
RHWM
(HSR Bit 4)
RPS
(HSR Bit 5)
RPE
(HSR Bit 6)
TUDR
(HSR Bit 7)
ROVR
(HSR Bit 13)
RABT
(HSR Bit 15)
TEND
(HSR Bit 0)
TLWM
(HSR Bit 2)
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Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
OR
HDLC
(IMSR Bit 3)
Mask
HDLC
Status Bit
(MSR Bit 3)
INT*
Hardware
Signal
DS3112

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