CY28442ZXC-2 Silicon Laboratories Inc, CY28442ZXC-2 Datasheet - Page 13

• Manufacturer Part Number: CY28442ZXC-2
• Description: Clock Generators & Support Products Calistoga
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28442ZXC-2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
FS_A, FS_B,FS_C
VDD Clock Gen
VTT_PW RGD#
PW RGD_VRM
Clock Outputs
Clock State
Clock VCO
SRC 100MHz
SRC 100MHz
PCI_STP#
PCI_STP#
PCI_F
PCI_F
PCI
PCI
State 0
Off
Off
0.2-0.3mS
Figure 11. PCI_STP# Deassertion Waveform
Tsu
State 1
Delay
Tsu
Figure 10. PCI_STP# Assertion Waveform
Figure 12. VTT_PWRGD# Timing Diagram
Tdrive_SRC
VTT_PW RGD#
SU
). (See
W ait for
On
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Sample Sels
State 2
On
State 3
VTT_PW RGD# is ignored
Device is not affected,
CY28442-2
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