CY28442ZXC-2 Silicon Laboratories Inc, CY28442ZXC-2 Datasheet
CY28442ZXC-2
Specifications of CY28442ZXC-2
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CY28442ZXC-2 Summary of contents
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Features ® • Compliant to Intel CK410M • Supports Intel Pentium-M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks • SRC ...
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Pin Definitions Pin No. Name 1 VDD_REF PWR 3.3V power supply for output 2 VSS_REF GND 33,32 CLKREQA#/SRCT6, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz CLKREQB#,SRCC6 7 VDD_PCI PWR 3.3V power supply for ...
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Pin Definitions (continued) Pin No. Name 48 VDDA2 PWR 3.3V power supply for PLL2 49 XOUT O, SE 14.318 MHz crystal output. 50 XIN 51 VSSA2 GND 52 REF1 53 FS_C_TEST_SEL/ REF0 54 CPU_STP PCI_STP ...
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Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Byte Count ...
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Control Registers Byte 0: Control Register 0 Bit @Pup Name 7 1 CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 6 1 SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C RESERVED Byte 1: Control Register 1 ...
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Byte 3: Control Register 3 Bit @Pup Name 7 0 SRC7 6 0 SRC6 5 0 SRC5 4 0 SRC4 3 0 SRC3 2 0 SRC2 1 0 SRC1 0 0 RESERVED Byte 4: Control Register 4 Bit @Pup Name ...
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Byte 5: Control Register 5 (continued) Bit @Pup Name 0 0 CPU[T/C]0 Byte 6: Control Register 6 Bit @Pup Name 7 0 TEST_SEL 6 0 TEST_MODE 5 0 RESERVED 4 1 REF 3 1 PCI, PCIF and SRC clock outputs ...
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Byte 8: Control Register 8 (continued) Bit @Pup Name 1 0 CLKREQ RESERVED Byte 9: Control Register 9 Bit @Pup Name 96_100 SEL 2 ...
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Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 14.31818 MHz AT Parallel The CY28442-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28442-2 to operate at the wrong frequency and violate the ppm ...
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CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active ...
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PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. ...
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CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock ...
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PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW ...
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VDD_A = 2.0V S0 Power Off Figure 13. Clock Generator Power-up/Run State Diagram Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient ...
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DC Electrical Specifications (continued) Parameter Description I High-impedance Output OZ Current C Input Pin Capacitance IN C Output Pin Capacitance OUT L Pin Inductance IN V Xin High Voltage XIH V Xin Low Voltage XIL I Dynamic Supply Current DD3.3V ...
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AC Electrical Specifications (continued) Parameter Description T 200-MHz CPUT and CPUC Absolute PERIODSSAbs period, SSC T CPUT/C Cycle to Cycle Jitter CCJ T CPU2_ITP Cycle to Cycle Jitter CCJ2 T CPU2_ITP to CPU0 Clock Skew SKEW2 CPUT ...
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AC Electrical Specifications (continued) Parameter Description T Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V PERIODSSAbs T PCIF and PCI high time HIGH T PCIF and PCI low time LOW PCIF/PCI rising and falling Edge Rate R ...
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Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the single-ended PCI outputs. 3.3V 2.4V 1.5V 0.4V Tr Figure 14. Single-ended PCI Lumped Load Configuration The following diagram shows the test load configuration for the ...
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... Ordering Information Part Number Lead-free CY28442ZXC-2 56-pin TSSOP CY28442ZXC-2T 56-pin TSSOP – Tape and Reel Package Diagrams 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use ...