CY28409OC Silicon Laboratories Inc, CY28409OC Datasheet
CY28409OC
Specifications of CY28409OC
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CY28409OC Summary of contents
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Clock Synthesizer with Differential SRC and CPU Outputs Features ® ® • Supports Intel Pentium 4-type CPUs • Selectable CPU frequencies • 3.3V power supply • Ten copies of PCI clocks • Five copies of 3V66 with one optional VCH ...
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Pin Description Pin No. Name Type 1, 2 REF(0: Reference Clock. 3.3V 14.318-MHz clock output. 4 XIN I 5 XOUT O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output. 41,44,47 CPUT(0:2) O, DIF CPU Clock Output. ...
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Table 1. Frequency Select Table (FS_A, FS_B) FS_A FS_B CPU 0 0 100 MHz 100/200 MHz 0 MID REF 200 MHz 100/200 MHz 1 0 133 MHz 100/200 MHz 1 MID Hi-Z Table 2. Frequency Select Table (FS_A, ...
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Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 20:27 Byte Count – 8 bits 28 Acknowledge from slave 29:36 Data byte 1 – 8 bits 37 Acknowledge from slave 38:45 Data byte 2 – ...
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Byte 0:Control Register 0 (continued) Bit @Pup Name 3 Externally PCI_STP# Selected 2 Externally CPU_STP# Selected 1 Externally FS_B Selected 0 Externally FS_A Selected Byte 1: Control Register 1 Bit @Pup Name 7 0 SRCT, SRCC 6 1 SRCT, SRCC ...
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Byte 3: Control Register 3 (continued) Bit @Pup Name 5 1 PCI5 4 1 PCI4 3 1 PCI3 2 1 PCI2 1 1 PCI1 0 1 PCI0 Byte 4: Control Register 4 Bit @Pup Name 7 0 USB_48 6 1 ...
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Byte 6: Control Register 6 Bit @Pup Name 7 0 Reserved 6 0 Reserved 5 0 CPUC0, CPUT0 CPUC1, CPUT1 CPUC2, CPUT2 4 0 SRCT, SRCC 3 0 Reserved 2 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP 1 1 REF_1 0 ...
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Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
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PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and ...
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PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ...
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FS_A, FS_B VTT_PWRGD# PWRGD_VRM 0.2-0.3 ms VDD Clock Gen Delay Clock State State 0 State 1 Off Clock Outputs Off Clock VCO VDDA = 2.0V S0 Power Off Figure 10. Clock Generator Power-up/Run State Diagram Rev 1.0, November 22, 2006 ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications (continued) Parameter Description CPU at 0.7V T CPUT and CPUC Duty Cycle DC T 100-MHz CPUT and CPUC Period PERIOD T 133-MHz CPUT and CPUC Period PERIOD T 200-MHz CPUT and CPUC Period PERIOD T Any CPUT/C ...
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AC Electrical Specifications (continued) Parameter Description PCIF and PCI rise and fall times Any PCI clock to Any PCI clock Skew Measurement at 1.5V SKEW T PCIF and PCI Cycle to Cycle Jitter CCJ ...
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... SSOP – Tape and Reel CY28409ZC 56-pin TSSOP CY28409ZCT 56-pin TSSOP – Tape and Reel PB-Free CY28409OXC 56-pin SSOP CY28409OCXT 56-pin SSOP – Tape and Reel CY28409ZXC 56-pin TSSOP CY28409ZXCT 56-pin TSSOP – Tape and Reel Rev 1.0, November 22, 2006 Ω ...
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Package Drawings and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear ...