STA304 STMicroelectronics, STA304 Datasheet - Page 22

• Manufacturer Part Number: STA304
• Description: Audio DSPs Digital Audio Proc
• Manufacturer: STMicroelectronics

Specifications of STA304

• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STA304
13.3 Tone Control Register (add. 08h)
This register support tone controls (bass and treble). The step size is 2dB. Writing a 0000h corresponds to
+12dB of gain. Center frequencies (from which gains are measured) are 160Hz for Bass and 5,000Hz for Treble.
The default value is 0F0Fh, which corresponds to bypass of bass or treble gain. The tone feature is implemented
only on the L and R front channel.
13.4 Powerdown Ctrl/Staus Register (PCSR) : add. 26h
NOTE: Bits D0..D3 will be masked to the showed value before writing into the RAM registers, other bits will simply pass through.
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EAPD
D15
D15
X
BIT
12
13
15
D14
D14
X
TR3... TR0 or BA3... BA0
R/W
R/W
R/W
R/W
D13
PR5
D13
X
RST
D12
PR4
0
0
1
D12
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
X
NAME
D11
BA3
EAPD
PR4
PR5
D11
BA2
D10
D10
Setting this bit to 1 the BIT_CLK and the SDATA_IN signal will be fixed to the
digital low level. To resume the normal operation either an hardware reset or a
softReset must be performed.
In order to set the device in a powerdown-like condition this bit must be set to 1.
This will stop the device internal clock: only the PLL and AC`97, I
still be running. DSP should start power-down sequence in order to accomplish
this request.
The value of this bit should be checked by the DSP in order to recognize an
external power amplifier power-down request. As a consequence the DSP
should start the power-down sequence (volume fade-out)
BA1
D9
D9
BA0
D8
+12 dB of gain
+10 dB of gain
Bypass
D8
-10 dB of gain
-12 dB of gain
+8 dB of gain
+6 dB of gain
+4 dB of gain
+2 dB of gain
+1 dB of gain
-1 dB of gain
-2 dB of gain
-4 dB of gain
-6 dB of gain
-8 dB of gain
0 dB of gain
D7
X
D7
D6
X
D6
DESCRIPTION
D5
X
D5
D4
Function
X
D4
TR3
D3
D3
1
TR2
D2
D2
1
TR1
2
D1
C clocks will
D1
1
TR0
D0
D0
0