LTC4253AIGN Linear Technology, LTC4253AIGN Datasheet - Page 21

• Manufacturer Part Number: LTC4253AIGN
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4253/
LTC4253A’s V
mended. The drawing in Figure 7 illustrates the correct
way of making connections between the LTC4253/
LTC4253A and the sense resistor. PCB layout should be
balanced and symmetrical to minimize wiring errors. In
addition, the PCB layout for the sense resistor should
include good thermal management techniques for optimal
sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
V
slower rate as set by the V
point 2, V
UV > V
V
SENSE < V
all conditions are met, initial timing starts and the TIMER
TRACK WIDTH W:
ON 1 OZ COPPER
OUT
OVHST
0.03" PER AMP
Figure 7. Making PCB Connections to the Sense Resistor
and DRAIN. V
UVHI
for the LTC4253A), RESET < 0.8V, GATE < V
IN
CURRENT FLOW
CB
FROM LOAD
exceeds V
(V
, SS < 20 • V
UV
W
EE
for the LTC4253A), OV < V
and SENSE pins are strongly recom-
IN
U
LKO
and the PWRGD signals follow at a
SENSE
SENSE RESISTOR
TO
and the internal logic checks for
U
OS
IN
, and TIMER < V
bypass capacitor. At time
V
TO
EE
W
TO –48V BACKPLANE
CURRENT FLOW
OVLO
TMRL
U
. When
4253 F07
(V
GATEL
OV
–
,
capacitor is charged by a 5µA current source pull-up. At
time point 3, TIMER reaches the V
initial timing cycle terminates. The TIMER capacitor is
quickly discharged. At time point 4, the V
reached and the conditions of GATE < V
and SS < 20 • V
up cycle begins. SS ramps up as dictated by R
in Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • V
GATE, 50µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current flows into the load ca-
pacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed, the SENSE voltage is regulated at V
(Equation 7) and soft-start limits the slew rate of the load
current. If the SENSE voltage (V
V
activates. The TIMER capacitor, C
(200µA + 8 • I
nears full charge, load current begins to decline. At time
point 8, the load current falls and the SENSE voltage drops
below V
the GATE pin ramps further. At time point 9, the SENSE
voltage drops below V
by a 5µA discharge cycle (cool-off). The duration between
time points 7 and 9 must be shorter than one circuit
breaker delay to avoid fault time-out during GATE ramp-
up. When GATE ramps past the V
point A, PWRGD1 pulls low. At time point B, GATE reaches
its maximum voltage as determined by V
A, SQTIMER starts its ramp-up to 4V. Having satisfied the
requirement that PWRGD1 is low for more than one t
PWRGD2 pulls low after EN2 pulls high above the V
threshold at time point C. This sets off the second SQTIMER
ramp-up. Having satisfied the requirement that PWRGD2
is low for more than one t
pulls high at time point D.
CB
threshold at time point 7, circuit breaker TIMER
ACL
(t). The analog current limit loop shuts off and
DRN
OS
LTC4253/LTC4253A
must be satisfied before the GATE start-
) current pull-up. As the load capacitor
CB
SQT
, the fault TIMER ends, followed
, PWRGD3 pulls low after EN3
SENSE
GATEH
TMRH
T
GATEL
, is charged by a
OS
– V
threshold and the
threshold at time
TMRL
. Upon releasing
IN
EE
, SENSE < V
. At time point
) reaches the
threshold is
SS
• C
21
425353afc
SS
ACL
SQT
(as
(t)
CB
IH
,