LTC4253AIGN Linear Technology, LTC4253AIGN Datasheet - Page 18

• Manufacturer Part Number: LTC4253AIGN
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4253/LTC4253A
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to V
SENSE exceeds 50mV, the CB comparator activates the
200µA TIMER pull-up. At 100mV (60mV for the LTC4253A)
the ACL amplifier servos the MOSFET current, and at
200mV the FCL comparator abruptly pulls GATE low in an
attempt to bring the MOSFET current under control. If any
of these conditions persists long enough for TIMER to
charge C
shut down and pull GATE low.
If the SENSE pin encounters a voltage greater than V
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
needs time to discharge GATE to the threshold of the
MOSFET. For a mild overload the ACL amplifier can control
the MOSFET current, but in the event of a severe overload
the current may overshoot. At SENSE = 200mV the FCL
comparator takes over, quickly discharging the GATE pin
to near V
amplifier takes over. All the while TIMER is running. The
effect of FCL is to add a nonlinear response to the control
loop in favor of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE under-
shoots. A zero in the loop (resistor R
gate capacitor) helps the ACL amplifier to recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 5. Initially the current overshoots
the analog current limit level of V
as the GATE pin works to bring V
The overshoot glitches the backplane in the negative direc-
tion and when the current is reduced to 100mV/R
backplane responds by glitching in the positive direction.
18
T
EE
to 4V (see Equation 3), the LTC4253/LTC4253A
potential. FCL then releases, and the ACL
U
U
GS
SENSE
under control (trace 3).
W
C
= 200mV (trace 2)
in series with the
U
EE
. When
S
, the
ACL
,
TIMER commences charging C
current limit loop maintains the fault current at 100mV/R
which in this case is 5A (trace 2). Note that the backplane
voltage (trace 1) sags under load. Timer pull-up is accel-
erated by V
PWRGD signals pull high, the load current drops to zero
and the backplane rings up to over 100V. The transient
associated with the GATE turn-off can be controlled with
a snubber to reduce ringing and a transient voltage sup-
pressor (such as Diodes Inc. SMAT70A) to clip off large
spikes. The choice of RC for the snubber is usually done
experimentally. The value of the snubber capacitor is
usually chosen between 10 to 100 times the MOSFET
C
tween 3Ω to 100Ω.
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 5 trace 1, can
rob charge from output capacitors on the adjacent card.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4253/LTC4253A are used by
the other cards, they respond by limiting the inrush
current to a value of V
capacitors will recharge long before C
OSS
. The value of the snubber resistor is typically be-
Figure 5. Output Short-Circuit Behavior of LTC4253
–48RTN
200mV
SENSE
0.5ms
0.5ms
0.5ms
0.5ms
TIMER
GATE
50V
10V
5V
OUT
. When C
TO CURRENT OVERSHOOT
SUPPLY RING OWING
ACL
ONSET OF OUTPUT
SHORT-CIRCUIT
FAST CURRENT
LIMIT
T
ANALOG
CURRENT LIMIT
reaches 4V, GATE turns off, the
C
/R
TIMER
S
. If C
RAMP
T
(trace 4) while the analog
SUPPLY RING OWING
TO MOSFET TURN-OFF
T
is sized correctly, the
LATCH OFF
T
4253 F05
times out.
TRACE 1
TRACE 2
TRACE 3
TRACE 4
425353afc
S
,