LTC4253AIGN Linear Technology, LTC4253AIGN Datasheet - Page 15

• Manufacturer Part Number: LTC4253AIGN
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
The resistive divider values shown set a standing current
of slightly more than 100µA and define an impedance at
UV/OV of 30kΩ. In most applications, 30kΩ impedance
coupled with 300mV UV hysteresis make the LTC4253
insensitive to noise. If more noise immunity is desired,
add a 1nF to 10nF filter capacitor from UV/OV to V
The separate UV and OV pins can be used for wider
operating range such as 35.6V to 76.3V range as shown in
Figure 2. Other combinations are possible with different
resistors arrangement.
UV/OV COMPARATORS (LTC4253A)
A UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 71V when
connected together as in Figure 3. A divider (R1, R2) is
used to scale the supply voltage. Using R1 = 392k and R2
= 30.1k gives a typical operating range of 43.2V to 71.4V.
The undervoltage shutdown and overvoltage recovery
thresholds are then 38.6V and 69.9V. 1% divider resistors
are recommended to preserve threshold accuracy.
The R1-R2 divider values shown in Figure 3 set a stand-
ing current of slightly more than 100µA and define an
impedance at UV/OV of 28kΩ. In most applications,
28kΩ impedance coupled with 324mV UV hysteresis
makes the LTC4253A insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor
from UV/OV to V
UV low-to-high (V
UV high-to-low (V
OV low-to-high (V
OV high-to-low (V
EE
.
U
UV
UV
OV
OV
) = 3.08V
) = 5.09V
– V
– V
U
UVHST
OVHST
) = 2.756V
) = 4.988V
W
U
EE
.
The UV and OV pins can also be used for a wider operating
range by adding a resistor between UV and OV as shown
in Figure 2 for the LTC4253. Other combinations are
possible with different resistor arrangements.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
the UV comparator immediately shuts down the LTC4253/
LTC4253A, pulls the MOSFET gate low and resets the three
latched PWRGD signals high.
An overvoltage condition is detected by the OV compara-
tor and pulls GATE low, thereby shutting down the load,
but it will not reset the circuit breaker TIMER and PWRGD
flags. Returning from the overvoltage condition will
restart the GATE pin if all the interlock conditions except
TIMER are met. Only during the initial timing cycle does OV
condition have an effect of resetting TIMER.
DRAIN
Connecting an external resistor, R
DRAIN pin allows V
drop) sensing without it being damaged by large voltage
transients. Below 5V, negligible pin leakage allows a
DRAIN low comparator to detect V
(V
sets the PWRGD flag.
When V
and the current flowing in R
This current is scaled up 8 times during a circuit breaker
fault before being added to the nominal 200µA. This
accelerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds V
ens the MOSFET heating duration.
DRNL
I
DRN
). This, together with the GATE low comparator,
OUT
≈
V
> V
OUT
DRNCL
−
R
LTC4253/LTC4253A
D
V
DRNCL
OUT
, the DRAIN pin is clamped at V
(MOSFET drain-source voltage
D
is given by:
DRNCL
D
, to this dual function
OUT
and effectively short-
less than 2.39V
15
425353afc
DRNCL
(1)