LTC3780EG Linear Technology, LTC3780EG Datasheet - Page 24

• Manufacturer Part Number: LTC3780EG
• Description: IC,SMPS CONTROLLER,CURRENT-MODE,CMOS,SSOP,24PIN,PLASTIC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC3780
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 65mV.
C
In this mode, the maximum output current peak is:
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 68mV.
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
• Place C
• Use immediate vias to connect the components (in-
• Use planes for V
• Flood all unused areas on all layers with copper. Flood-
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3780. These items are also illustrated in Figure 11.
• Segregate the signal and power grounds. All small
24
OUT
it should be as close as possible to the layer with power
MOSFETs.
area. Place C
compact area.
cluding the LTC3780’s SGND and PGND pins) to the
ground plane. Use several large vias for each power
component.
filtering and to keep power losses low.
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to any
DC net (V
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
sources of Switch B and Switch C.
I
OUT PEAK MAX BUCK
is chosen to filter the square current in Boost mode.
,
IN
(
, Switch A, Switch B and D2 in one compact
IN
or GND).
OUT
,
U
IN
, Switch C, Switch D and D1 in one
and V
)
=
U
12
5
OUT
• •
5 1 13
to maintain good voltage
(
W
+
%
)
=
U
13 6
.
A
• Place Switch B and Switch C as close to the controller
• Keep the high dV/dT SW1, SW2, BOOST1, BOOST2, TG1
• The path formed by Switch A, Switch B, D2 and the C
• The output capacitor (–) terminals should be connected
• Connect the INTV
• Connect the top driver boost capacitor C
• Connect the input capacitors C
• Connect V
• Route SENSE
• Connect the I
as possible, keeping the PGND, BG and SW traces
short.
and TG2 nodes away from sensitive small-signal nodes.
capacitor should have short leads and PC trace lengths.
The path formed by Switch C, Switch D, D1 and the C
capacitor also should have short leads and PC trace
lengths.
as close as possible the (–) terminals of the input
capacitor.
to the INTV
BOOST1 and SW1 pins. Connect the top driver boost
capacitor C
C
carry the MOSFET AC current in Boost and Buck mode.
nals of C
decoupling capacitor should be as close as possible to
the LTC3780 SGND pin. The R2 connection should not
be along the high current or noise paths, such as the
input capacitors.
mum PC trace spacing. The filter capacitor between
SENSE
the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
IC, between I
tor helps to filter the effects of PCB noise and output
voltage ripple voltage from the compensation loop.
OUT
close to the power MOSFETs. These capacitors
+
and SENSE
OSENSE
OUT
CC
B
TH
closely to the BOOST2 and SW2 pins.
TH
–
and PGND pins.
and signal ground. A small V
and SENSE
and the signal ground pins. The capaci-
pin compensation network close to the
CC
pin resistive dividers to the (+) termi-
–
decoupling capacitor C
should be as close as possible to
+
leads together with mini-
IN
and output capacitors
A
closely to the
VCC
closely
OSENSE
OUT
3780f
IN