MT9V022I77ATC Aptina LLC, MT9V022I77ATC Datasheet - Page 52
![IC SENSOR IMAGE VGA COLOR 52IBGA](/photos/27/2/270273/mfg_mt9v022_series_sml.jpg)
MT9V022I77ATC
Manufacturer Part Number
MT9V022I77ATC
Description
IC SENSOR IMAGE VGA COLOR 52IBGA
Manufacturer
Aptina LLC
Type
CMOS Imagingr
Series
DigitalClarity®r
Specifications of MT9V022I77ATC
Pixel Size
6µm x 6µm
Active Pixel Array
752H x 480V
Frames Per Second
60
Voltage - Supply
3.3V
Package / Case
52-IBGA
Sensor Image Color Type
Color
Sensor Image Size Range
250,920 to 480,000Pixels
Sensor Image Size
752x480Pixels
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Package Type
IBGA
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1267
MT9V022I77ATC
MT9V022I77ATC
Appendix B – Power-On Reset and Standby Timing
Reset, Clocks, and Standby
Figure 49:
V
Two-Wire Serial I/F
PDF: 3295348826/Source:7478516499
MT9V022_DS - Rev.H 6/10 EN
V
DD ,
AA ,
MIN 10 SYSCLK cycles
SCLK
DATA OUTPUT
STANDBY
V
VAAPIX
D
DD
OUT
SYSCLK
RESET #
,
LVDS,
S
DATA
[9:0]
Power
up
Driven = 0
Power-up, Reset, Clock and Standby Sequence
Notes:
MIN 20 SYSCLK cycles
Active
There are no constraints concerning the order in which the various power supplies are
applied; however, the MT9V022 requires reset in order operate properly at power-up.
Refer to Figure 49 for the power-up, reset, and standby sequences.
1. All output signals are defined during initial power-up with RESET# held LOW without SYSCLK being
2. Before using two-wire serial interface, wait for 10 SYSCLK rising edges after RESET# is de-asserted.
3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before
4. In standby, all video data and synchronization output signals are High-Z.
5. In standby, the two-wire serial interface is not active.
non-Low-Power
active. To properly reset the rest of the sensor, during initial power-up, assert RESET# (set to LOW state)
for at least 750ns after all power supplies have stabilized and SYSCLK is active (being clocked). Driving
RESET# to LOW state does not put the part in a low power state.
entering standby mode. The user must supply enough SYSCLKs to allow a complete frame readout. See
Table 4, “Frame Time,” on page 13 for more information.
Pre-Standby
Note 3
STANDBY = 1
respond to
Does not
interface
serial
when
D
OUT
52
MIN 10 SYSCLK cycles
Low-Power
Standby
[9:0]
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Appendix B – Power-On Reset and Standby Timing
Wake
up
Aptina reserves the right to change products or specifications without notice.
non-Low-Power
MIN 10 SYSCLK cycles
©2005 Aptina Imaging Corporation. All rights reserved.
Active
Power
down