CYII5SC1300AB-QDC Cypress Semiconductor Corp, CYII5SC1300AB-QDC Datasheet - Page 23
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CYII5SC1300AB-QDC
Manufacturer Part Number
CYII5SC1300AB-QDC
Description
SENSOR IMAGE COLOR CMOS 84-LCC
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Specifications of CYII5SC1300AB-QDC
Pixel Size
6.7µm x 6.7µm
Active Pixel Array
1280H x 1024V
Frames Per Second
27
Voltage - Supply
3 V ~ 4.5 V
Package / Case
84-LCC
Sensor Image Color Type
Color
Sensor Image Size Range
>= 480,000Pixels
Sensor Image Size
1280x1024Pixels
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 65C
Package Type
CLCC
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package
84CLCC
Image Size
1280x1024 Pixels
Color Sensing
Color
Operating Temperature
0 to 65 °C
Operating Supply Voltage
3 to 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Global Shutter: Multiple Slope Integration
Use up to four different pixel reset voltages during multiple slope
operation in synchronous shutter mode. This is done by
uploading
KNEEPOINT_MSB/LSB/ENABLE before a new SS_START
pulse is applied.
Set bit KNEEPOINT_ENABLE high to do a pixel reset with a
lower voltage.
Set bits KNEEPOINT_MSB/LSB/ENABLE back to ‘0’ before the
SS_STOP pulse is applied. Every time an SS_START pulse is
applied, the integration time counter is reset.
The TIME_OUT signal cannot be used in multi-slope operation
to determine the location of the next SS_START or SS_STOP
pulse. External counters must be used for generating these
signals.
Table 22. Multiple Slope Register Settings
Document #: 38-05710 Rev. *H
Initial Setup
1st Register Upload
2nd Register Upload
3th Register Upload
4th Register Upload
new
values
MSB/LSB
00
01
10
11
00
to
Kneepoint
Figure 25. Multiple Slope Integration
register
Enable
0
1
1
1
0
bits
Upload the register after time T
affects the SS-sequencer resulting in a bad pixel reset. T
depends on the granularity of the SS-sequencer clock (see
Table
Table 23. T
T
registers.
Table 24. T
Parallel
Serial 3-wire
Granularity
upload
Interface Mode
N
× 128
× 256
× 32
× 64
GRAN
23).
depends on the interface mode used to upload the
stable
upload
= 5 × N
1280 × T
640 × T
160 × T
320 × T
for Different Granularity Settings
for Different Interface Modes
GRAN
T
stable
SYS_CLOCK
SYS_CLOCK
SYS_CLOCK
SYS_CLOCK
× T
(µs)
SYS_CLOCK
stable
= 16
CYII5SM1300AB
= 4
= 8
= 32
, otherwise, the change
T
GRAN_SS_SEQ
upload
MSB/LSB
Page 23 of 35
00
01
10
11
(µs)
1
8
stable
[+] Feedback