CYII4SM014KAA-GWC Cypress Semiconductor Corp, CYII4SM014KAA-GWC Datasheet - Page 8

• Manufacturer Part Number: CYII4SM014KAA-GWC
• Description: IC SENSOR IMAGE MONO 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM014KAA-GWC

• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Package / Case: 49-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Sensor Read Out Timing Diagrams
Row Sequencer
The row sequencer controls pulses to be given at the start of
each new line.
this sequence.
The signals to be controlled at each row are:
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Document #: 38-05709 Rev. *D
CLK_YL and CLK_YR: These are the clocks of the YL and YR
shift register. They can be driven by the same signals and at a
continuous frequency. At every rising edge, a new row is being
selected.
SELECT: This signal connects the pixels of the currently
sampled line with the columns. It is important that PC and
SELECT are never active together.
PC: An initialization pulse that needs to be given to precharge
the column.
SHS (Sample & Hold pixel Signal): This signal controls the track
and hold circuits in the column amplifiers. It is used to sample
the pixel signal in the columns. (0 = track ; 1 = hold).
RESET: This pulse resets the pixels of the row that is currently
being selected. In rolling shutter mode, the RESET signal is
pulsed a second time to reset the row selected by the YR shift
register. For “reset black” dark reference signals, the reset
pulse can be pulsed also during the first PC pulse. Normally,
the rising edge of RESET and the falling edge of PC occur at
Figure 9
on page 9 shows the timing diagram for
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Figure 8. F Subsample Mode
m ode F - 1:12
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Figure 9
IBIS4-14000 image sensor and
timing specifications of the clocking scheme.
the same position. The falling edge of RESET lags behind the
rising PC edge.
SHR (Sample & Hold pixel Reset level): This signal controls
another track and hold circuit in the column amplifiers. It is used
to sample the pixel reset level in the columns (for double
sampling). (0 = track ; 1 = hold).
SYL (Select YL register): Selects the YL shift register to drive
the reset line of the pixel array.
SYR (Select YR register): Selects the YR shift register to drive
the reset line of the pixel array. For rolling shutter applications,
SYL and SYR are complementary. In full frame readout, both
registers may be selected together, only if it is guaranteed that
both shift registers point to the same row. This can reduce the
row blanking time.
SYNC_YR and SYNC_YL: Synchronization pulse for the YR
and YL shift registers. The SYNC_YR/SYNC_YL signal is
clocked in during a rising edge on CLK_YR/CLK_YL and resets
the YR/YL shift register to the first row. Both pulses are pulsed
only once each frame. The exact pulsing scheme depends on
the mode of use (full frame/ rolling shutter). A 200 ns setup time
applies. See
SYNC_X: Resets the column pointer to the first row. This has
to be done before the end of the first PC pulse in case the
previous line has not been read out completely.
on page 9 shows the basic timing diagram of the
Table 4 on page
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
9.
Table 4
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1
2
3
4
5
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7
8
9
on page 9 shows the
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