CYII4SM014KAA-GWC Cypress Semiconductor Corp, CYII4SM014KAA-GWC Datasheet - Page 14

• Manufacturer Part Number: CYII4SM014KAA-GWC
• Description: IC SENSOR IMAGE MONO 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM014KAA-GWC

• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Package / Case: 49-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Pin Configuration
Table 8
Table 8. Pinout Configuration
Document #: 38-05709 Rev. *D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin #
lists the pin configuration of the IBIS4-14000.
OBIAS
GND
OUT3
GND
OUT4
VDD
GND
OUT2
GND
OUT1
GND
PHDIODE
SYNC_Y
GNDAB
GND
CLK_YR
SYR
SYNC_YR
VDDARRAY Pixel array power supply (= pin 26).
VDDARRAY Pixel array power supply (= pin 25).
SYL
DARKREF
TEMP1
CLK_Y
TEMP2
VDD
VDDR
SYNC_YL
Name
Bias current output amplifiers.
Ground for output 3.
Output 3.
Ground for output 4.
Output 4.
Power supply.
Ground.
Output 2.
Ground for output 2.
Output 1.
Ground for output 1.
Offset level of output signal.
Temperature sensor.
Located near the output amplifiers (pixel
4536, 0) near the stitch line).
Photodiode output.
Yields the equivalent photocurrent of 250 x
50 pixels. Diode is located right under the
pad.
Y clock for switchboard.
Y SYNC pulse for switchboard.
Temperature sensor.
Located near pixel (24,0).
Anti-blooming reference level (= pin 33).
Ground.
Power supply.
Power supply for reset line drivers
Clock of YR shift register.
Activate YR shift register for driving of reset
and select line of pixel array.
Sets the YR shift register to row 1.
Sets the YL shift register to row 1.
Activate YL shift register for driving of reset
and select line of pixel array.
Function
Figure 16
on page 21 shows the assignment of pin numbers on the package.
Connect with 10k Ω to VDD and decouple with 100 nF to
GND.
Nominal 3.3V
0V
Typ. 2.6V. min. 1.7V max. 3V
Any voltage above GND forward biases the diode.
Connect to GND if not used.
Reverse biased by any voltage above GND
Connect to GND if not used.
Clocks on rising edge
Connect to CLK_YL (or drive identically)
Low active: synchronous sync on rising edge of CLK_Y
Connect to SYNC_YL (or drive identically)
Any voltage above GND forward biases the diode.
Connect to GND if not used.
Typ. 0V. Set to 1.5V for improved anti-blooming.
0V
Nominal 3.3V
Nominal 4V
Connected on-chip to pin 30
Shifts on rising edge.
High active. Exact pulsing pattern see timing diagram.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected!
Low active. Synchronous sync on rising edge of CLK_YR
200 ns setup time
3V
3V
Low active. Synchronous sync on rising edge of CLK_YL
200 ns setup time.
High active. Exact pulsing pattern see timing diagram.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected.
Comment
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
Page 14 of 27
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