VV6501C001 STMicroelectronics, VV6501C001 Datasheet - Page 19

no-image

VV6501C001

Manufacturer Part Number
VV6501C001
Description
IC SENSOR COLOR VGA CMOS 36CLCC
Manufacturer
STMicroelectronics
Type
CMOS Imagingr
Datasheet

Specifications of VV6501C001

Pixel Size
5.6µm x 5.6µm
Active Pixel Array
640H x 480V
Frames Per Second
30
Voltage - Supply
3V, 5V
Package / Case
36-CLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-3883
VV6501C001

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
VV6501C001
Manufacturer:
UDT
Quantity:
1 000
VV6501
3.1.10 Sensor clock and frame rate control
Dark calibration algorithm
The dark line monitoring logic accumulates a number of dark pixels, calculates an average and then
compares this average with the appropriate black level. There is a bit in serial register 45 which
determines whether the offset applied is the user-programmable value from serial register 44, or the
value calculated by the offset cancellation processor.
The dark offset cancellation algorithm accumulates data from the dark lines which is input to a leaky
integrator and an appropriate offset is calculated.
Following an exposure/gain change, on power up or when going out of suspend mode, the history in
the dark calibration leaky integrator is reset to the incoming value as the previously stored value will
be out of date.
User control
The serial interface allows the user the following additional controls:
The frame rate is determined by both the input sensor clock and some additional registers under
user control.
Sensor clock
The sensor requires a single-ended clock input. A 24MHz clock is required to generate 30 frames
per second VGA images. The results is a pixel rate of 12MHz.
Slower frame rates
In order to achieve slower frame-rates the user has a number of options:
Clock divider
The sensor contains a 4-bit register with which the user selects the clock divider setting (N).
gives the mapping between the clk_div value and the divider ratio.
Accumulate dark pixels, calculate dark pixel average and report, but do not apply anything to
data stream
Accumulate dark pixels, calculate dark pixel average, report and apply internally calculated
offset to data stream
Accumulate dark pixels, calculate dark pixel average and report, but apply a SIF supplied offset
increase the inter-frame time by adding blank line (via SIF register)
apply a slower external clock
divide down the external clock using the sensor internal clock divider (via SIF register)
Table 5: User programmable clock divider values
0000 [default]
clk_div[3:0]
001X
010X
011X
100X
0001
divide by
10
1
2
4
6
8
Functional Description
Table 5
19/60

Related parts for VV6501C001