KSZ8851-16MQL Micrel Inc, KSZ8851-16MQL Datasheet - Page 39

• Manufacturer Part Number: KSZ8851-16MQL
• Description: Single Ethernet Port + Generic (16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MQL

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-3292 - BOARD EVALUATION KSZ8851-16MLL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3253

Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
Driver Routine for Receive Packet from KSZ8851M to Host Processor
The software driver receives data packet frames from the KSZ8851M device either as a result of polling or an interrupt
based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt vector
table.
If your system has OS support, to minimize interrupt lockout time, the interrupt service routine should handle at interrupt
level only those tasks that require minimum execution time, such as error checking or device status change. The routine
should queue all the time-consuming work to transfer the packet from the KSZ8851M RXQ into system memory at task
level. The following Figure 10 shows the step-by-step for receive packets from KSZ8851M to host processor.
Note: Each DMA read operation from the host CPU to read RXQ frame buffer, the first read data (byte in 8-bit bus mode,
word in 16-bit bus mode and double word in 32-bit bus mode) is dummy data and must be discarded by host CPU.
Afterward, host CPU must read each frame data to align with double word boundary at end. For example, the host CPU
has to read up to 68 bytes if received frame size is 65 bytes.
Figure 10. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram
August 2009
39
M9999-083109-2.0