KSZ8851-16MQL Micrel Inc, KSZ8851-16MQL Datasheet - Page 17

• Manufacturer Part Number: KSZ8851-16MQL
• Description: Single Ethernet Port + Generic (16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MQL

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-3292 - BOARD EVALUATION KSZ8851-16MLL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3253

Pin Description for 32-Bit
August 2009
Micrel, Inc.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCAN_EN
Pin Name
TEST_EN
P1LED2
P1LED0
P1LED1
LDEVN
VDDIO
INTRN
DGND
PME
NC
NC
NC
NC
NC
NC
NC
Ipu/O
Ipu/O
Ipu/O
Type
Opu
Gnd
Opu
Opu
—
—
—
—
—
—
—
P
I
I
Pin Function
Test Enable
For normal operation, pull-down this pin-to-ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this pin-to-ground.
Port 1 LED indicators
LED is ON when output is LOW; LED is OFF when output is HIGH.
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27.
No Connect.
No Connect.
No Connect.
Digital ground
3.3V, 2.5V or 1.8V digital V
No Connect.
No Connect.
No Connect.
Power Management Event: It is asserted (low or high depends on polarity set in PMECR
register) when one of the wake-on-LAN events is detected by KSZ8851M. The
KSZ8851M is requesting the system to wake up from low power mode.
No Connect.
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set.
Local Device Not
Active Low output signal, asserted when AEN is Low and A7-A1 decode to the
KSZ8851M right address register. LDEVN is a combinational decode of the Address and
AEN signal.
P1LED3
P1LED2
P1LED1
P1LED0
P1LED3
P1LED2
P1LED1
P1LED0
2
2
1
defined as follows:
17
DDIO
Chip Global Control Register: CGCR
bit [15,9]
[0,0] Default
—
Link/Act
Full duplex/Col
Speed
Reg. CGCR bit [15,9]
[1,0]
Act
Link
Full duplex/Col
Speed
input power supply for IO with well decoupling capacitors.
[0,1]
—
100Link/Act
10Link/Act
[1,1]
—
—
—
—
Full duplex
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0