KSZ8842-PMBL AM Micrel Inc, KSZ8842-PMBL AM Datasheet - Page 33

• Manufacturer Part Number: KSZ8842-PMBL AM
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL AM

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3348

Micrel, Inc.
For ingress rate limiting, KSZ8842-PMQL/PMBL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. The KSZ8842-PMQL/PMBL counts the data rate from those selected type of
frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per frame base to generate smooth, non-bursty egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
MAC Filtering Function
Use the static table to assign a dedicated MAC address to a specific port. When a unicast MAC address is not recorded
in the static table, it is also not learned in the dynamic MAC table. The KSZ8842-PMQL/PMBL includes an option that
can filter or forward unicast packets for an unknown MAC address. This option is enabled by SGCR7[7].
The unicast MAC address filtering function is useful in preventing the broadcast of unicast packets that could degrade
the quality of this port in applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8842-PMQL/PMBL operates as a managed switch or a repeater, however it cannot be used as an unmanaged
switch.
EEPROM Interface
The external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information
such as the host MAC address and ID, (for example, 93C46 or 93C66 EEPROM devices.)
If the EEEN pin/ball is pulled high, the KSZ8842-PMQL/PMBL performs an automatic read of the external EEPROM
words 0H to 6H after the de-assertion of Reset. The EEPROM values are placed in certain host-accessible registers.
EEPROM read/write functions can also be performed by software read/writes to the EEPCR registers.
The KSZ8842-PMQL/PMBL EEPROM format is given below.
Loop back Support
The KSZ8842-PMQL/PMBL provides loop back support for remote diagnostic of failure. In loop back mode, the speed
at both PHY ports will be set to 100BASE-TX full-duplex mode. Two types of loop back are supported: Far-end Loop
back and Near-end (Remote) Loop back.
Far-end Loop back:
Far-end loop back is conducted between the KSZ8842-PMQL/PMBL’s two PHY ports. The loop back path starts at the
“Originating” PHY. The originating PHY port’s receive inputs (RXP/RXM), wrap around at the “loop back” PHY port’s
PMD/PMA, and ends at the “Originating” PHY port’s transmit outputs (TXP/TXM).
October 2007
WORD
7H-3FH
0H
1H
2H
3H
4H
5H
6H
15
Host MAC Address Byte 2
Host MAC Address Byte 4
Host MAC Address Byte 6
Not used by KSZ8842-PMQL/PMBL (available for user to use)
Table 7. EEPROM Format
Subsystem Vendor ID
Subsystem ID
33
8
Reserved
Reserved
7
Host MAC Address Byte 1
Host MAC Address Byte 3
Host MAC Address Byte 5
KSZ8842-PMQL/PMBL
0
M9999-100207-1.5