EPM7160STC100-6N Altera, EPM7160STC100-6N Datasheet - Page 48
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EPM7160STC100-6N
Manufacturer Part Number
EPM7160STC100-6N
Description
MAX 7000/S/AE/B
Manufacturer
Altera
Datasheet
1.EPM7160STC100-6N.pdf
(66 pages)
Specifications of EPM7160STC100-6N
Family Name
MAX 7000S
Memory Type
EEPROM
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
166.7MHz
Propagation Delay Time
6ns
Number Of Logic Blocks/elements
10
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
48
t
t
t
Symbol
t
t
t
t
t
t
t
t
t
t
Symbol
CLR
PIA
LPA
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2)
Table 35. EPM7192S External Timing Parameters (Part 1 of 2)
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
The f
Operating conditions: V
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
The t
running in the low-power mode.
LPA
MAX
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Register clear time
PIA delay
Low-power adder
parameter must be added to the t
values represent the highest frequency for pipelined data.
Parameter
Parameter
CCIO
Tables 35
= 3.3 V ± 10% for commercial and industrial use.
(7)
(8)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
and
Conditions
LAD
36
, t
show the EPM7192S AC operating conditions.
LAC
, t
Min Max Min Max Min Max Min Max
IC
, t
-6
EN
Min
4.1
0.0
3.0
0.0
3.0
3.0
1.0
11.0
, t
2.4
1.6
SEXP
-7
Max
, t
7.5
7.5
4.7
ACL
Note (1)
Note (1)
-7
, and t
Speed Grade
Speed Grade
10.0
Min
7.0
0.0
3.0
0.5
4.0
4.0
2.0
3.0
2.0
CPPW
-10
Table
LAD
Max
10.0
10.0
5.0
parameters for macrocells
-10
parameter into the signal
11.0
14. See
3.0
1.0
Min
11.0
0.0
3.0
0.0
5.0
5.0
4.0
Altera Corporation
Figure 13
-15
-15
Max
LPA
15.0
15.0
8.0
13.0
parameter
4.0
2.0
for more
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns