EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 14

• Manufacturer Part Number: EP9307-CRZR
• Description: IC Universal Platform ARM9 SOC Prcessor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZR

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-LFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5809834A

EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements.
14
• T
• CVDD = VDD_PLL = 1.8V
• RVDD = 3.3 V
• All grounds = 0 V
• Logic 0 = 0 V, Logic 1 = 3.3 V
• Output loading = 50 pF
• Timing reference levels = 1.5 V
• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between
33 MHz and 100 MHz (92 MHz for industrial conditions).
A
= 0 to 70° C

Copyright 2010 Cirrus Logic (All Rights Reserved)
Bus/Signal Omission
Valid Bus to Tristate
Figure 1. Timing Diagram Drawing Key
Undefined/Invalid
High/Low to High
Bus Change
High to Low
Bus Valid
Clock
DS667F2