EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 75

Cyclone III

EP3C16F484A7N

Manufacturer Part Number
EP3C16F484A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet

Specifications of EP3C16F484A7N

Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / Rohs Status
Compliant

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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Cyclone III Device Family PLL Hardware Overview
© December 2009
f
Altera Corporation
Figure 5–7
Figure 5–7. External Clock Outputs for PLLs
Notes to
(1) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
(2) PLL#_CLKOUTp and PLL#_CLKOUTn pins are dual-purpose I/O pins that you can use as one single-ended or
Each pin of a differential output pair is 180° out of phase. The Quartus II software
places the NOT gate in your design into the I/O element to implement 180° phase
with respect to the other pin in the pair. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as well as LVDS,
LVPECL, differential HSTL, and differential SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
Cyclone III device family PLLs can drive out to any regular I/O pin through the
GCLK. You can also use the external clock output pins as general purpose I/O pins if
external PLL clocking is not required.
one differential clock output.
Figure
shows the external clock outputs for PLLs.
5–7:
Cyclone III Device I/O Features
PLL #
clkena 0
C0
C1
C2
C3
C4
PLL #_CLKOUTp
(1)
chapter.
PLL #_CLKOUTn
(2)
Cyclone III Device Handbook, Volume 1
clkena 1
(2)
(1)
5–11

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