EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 260
EP3C16F484A7N
Manufacturer Part Number
EP3C16F484A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C16F484A7N.pdf
(274 pages)
Specifications of EP3C16F484A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484A7N
Manufacturer:
ALTERA
Quantity:
717
Part Number:
EP3C16F484A7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
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11–6
Software Support
Cyclone III Device Handbook, Volume 1
CRC calculation time depends on the device and the error detection clock frequency.
Table 11–6
maximum clock frequencies for Cyclone III device family.
Table 11–6. CRC Calculation Time
Enabling the CRC error detection feature in the Quartus II software generates the
CRC_ERROR output to the optional dual purpose CRC_ERROR pin.
To enable the error detection feature using CRC, perform the following steps:
1. Open the Quartus II software and load a project using Cyclone III device family.
2. On the Assignments menu, click Settings. The Settings dialog box appears.
3. In the Category list, select Device. The Device page appears.
4. Click Device and Pin Options, as shown in
5. In the Device and Pin Options dialog box, click the Error Detection CRC tab.
6. Turn on Enable error detection CRC.
7. In the Divide error check frequency by box, enter a valid divisor as documented
8. Click OK.
Cyclone III
Cyclone III LS
Notes to
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
in
1
processes, voltages, and temperatures (PVT).
Table 11–5 on page
Table
The divisor value divides down the frequency of the configuration
oscillator output clock. This output clock is used as the clock source for the
error detection process.
lists the estimated time for each CRC calculation with minimum and
11–6:
Device
11–5.
EP3CLS100
EP3CLS150
EP3CLS200
EP3CLS70
EP3C120
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C5
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Minimum Time (ms)
Figure
(1)
15
23
31
45
42
42
79
79
5
5
7
9
11–2.
© December 2009 Altera Corporation
Maximum Time (s)
11.77
15.81
22.67
21.24
21.24
40.27
40.27
Software Support
2.29
2.29
3.17
4.51
7.48
(2)
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