EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 52
EP3C16F484A7N
Manufacturer Part Number
EP3C16F484A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C16F484A7N.pdf
(274 pages)
Specifications of EP3C16F484A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484A7N
Manufacturer:
ALTERA
Quantity:
717
Part Number:
EP3C16F484A7N
Manufacturer:
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3–16
Read or Write Clock Mode
Single-Clock Mode
Design Considerations
Read-During-Write Operations
Figure 3–14. Cyclone III Device Family Read-During-Write Data Flow
Cyclone III Device Handbook, Volume 1
write_a
read_a
Cyclone III device family M9K memory blocks can implement read or write clock
mode for FIFO and simple dual-port memories. In this mode, a write clock controls
the data inputs, write address, and wren registers. Similarly, a read clock controls the
data outputs, read address, and rden registers. M9K memory blocks support
independent clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Cyclone III device family M9K memory blocks can implement single-clock mode for
FIFO, ROM, true dual-port, simple dual-port, and single-port memories. In this mode,
you can control all registers of the M9K memory block with a single clock together
with clock enable.
This section describes designing with M9K memory blocks.
“Same-Port Read-During-Write Mode” on page 3–17
Write Mode” on page 3–18
configurations when reading from an address during a write operation at that same
address.
There are two read-during-write data flows: same-port and mixed-port.
shows the difference between these flows.
Port A
data in
Port A
data out
describe the functionality of the various RAM
Chapter 3: Memory Blocks in the Cyclone III Device Family
Port B
data in
Port B
data out
and
read_b
write_b
“Mixed-Port Read-During-
© December 2009 Altera Corporation
Mixed-port
data flow
Same-port
data flow
Design Considerations
Figure 3–14
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