DSPIC33FJ64MC804T-I/ML Microchip Technology, DSPIC33FJ64MC804T-I/ML Datasheet - Page 313
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DSPIC33FJ64MC804T-I/ML
Manufacturer Part Number
DSPIC33FJ64MC804T-I/ML
Description
16-bit DSC, 64KB Flash,Motor,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC804T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ64MC804T-I/MLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC804T-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- Current page: 313 of 436
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27.0
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
FIGURE 27-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note 1: This data sheet summarizes the features
Parallel Master Port
Note 1: 28-pin devices do not have PMA<10:2>.
2: Some registers and associated bits
PARALLEL MASTER PORT
(PMP)
dsPIC33F
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 35. Parallel
Master Port (PMP)”(DS70299) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
PMP MODULE OVERVIEW
dsPIC33FJ32MC302/304,
web
PMA<0>
PMALL
PMA<1>
PMALH
PMA<10:2>
PMCS1
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<10:8>
PMA<14>
family
and
site
(1)
of
in
Microcontroller
Key features of the PMP module include:
• Fully Multiplexed Address/Data Mode
• Demultiplexed or Partially Multiplexed Address/
• One Chip Select Line
• Programmable Strobe Options:
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support:
• Programmable Wait States
• Selectable Input Voltage Levels
- 16 bits of address
Data mode:
- Up to 11 address lines with single Chip Select
- Up to 12 address lines without Chip Select
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
Up to 11-Bit Address
8-Bit Data
LCD
Address Bus
Data Bus
Control Lines
Buffer
FIFO
DS70291E-page 313
EEPROM
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