DSPIC33FJ64MC804T-I/ML Microchip Technology, DSPIC33FJ64MC804T-I/ML Datasheet - Page 204
![16-bit DSC, 64KB Flash,Motor,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ64MC804T-I/ML
Manufacturer Part Number
DSPIC33FJ64MC804T-I/ML
Description
16-bit DSC, 64KB Flash,Motor,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC804T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ64MC804T-I/MLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC804T-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- Current page: 204 of 436
- Download datasheet (6Mb)
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
14.1
REGISTER 14-1:
DS70291E-page 204
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
ICTMR
R/W-0
U-0
—
Input Capture Registers
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1 = Input capture module halts in CPU Idle mode
0 = Input capture module continues to operate in CPU Idle mode
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
ICM<2:0>: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling)
000 = Input capture module turned off
R/W-0
U-0
—
ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2, 7 or 8)
(Rising edge detect only, all other control bits are not applicable).
(ICI<1:0> bits do not control interrupt generation for this mode).
ICI<1:0>
W = Writable bit
‘1’ = Bit is set
ICSIDL
R/W-0
R/W-0
R-0, HC
ICOV
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0, HC
ICBNE
U-0
—
HC = Cleared in Hardware
R/W-0
U-0
—
© 2011 Microchip Technology Inc.
x = Bit is unknown
ICM<2:0>
R/W-0
U-0
—
R/W-0
U-0
—
bit 8
bit 0
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