DSPIC33FJ64MC804T-I/ML Microchip Technology, DSPIC33FJ64MC804T-I/ML Datasheet - Page 301
![16-bit DSC, 64KB Flash,Motor,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ64MC804T-I/ML
Manufacturer Part Number
DSPIC33FJ64MC804T-I/ML
Description
16-bit DSC, 64KB Flash,Motor,CAN, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC804T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ64MC804T-I/MLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC804T-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- Current page: 301 of 436
- Download datasheet (6Mb)
REGISTER 25-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1:
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
RTCEN
R/W-0
R/W-0
2:
3:
(2)
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
RTCEN: RTCC Enable bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
HALFSEC: Half-Second Status bit
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC output enabled
0 = RTCC output disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers;
the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
11 =Reserved
10 =MONTH
01 =WEEKDAY
00 =MINUTES
RTCVAL<7:0>:
11 =YEAR
10 =DAY
01 =HOURS
00 =SECONDS
R/W-0
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid
U-0
—
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
‘1’ = Bit is set
W = Writable bit
RTCWREN
R/W-0
R/W-0
(2)
RTCSYNC HALFSEC
R/W-0
R-0
(3)
CAL<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R-0
(3)
RTCOE
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
RTCPTR<1:0>
(1)
DS70291E-page 301
R/W-0
R/W-0
bit 8
bit 0
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