DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 306
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
TABLE A-1:
DS70283H-page 306
Section 18.0 “Inter-Integrated
Circuit™ (I2C™)”
Section 19.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Section 20.0 “10-bit/12-bit
Analog-to-Digital Converter (ADC)”
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 17.3 “I
• 17.4 “Baud Rate Generator” (retained Figure 15-1: I
• 17.5 “I
• 17.6 “Slave Address Masking”
• 17.7 “IPMI Support”
• 17.8 “General Call Address Support”
• 17.9 “Automatic Clock Stretch”
• 17.10 “Software Controlled Clock Stretching (STREN = 1)”
• 17.11 “Slope Control”
• 17.12 “Clock Arbitration”
• 17.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration”
• 17.14 “Peripheral Pin Select Limitations”
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 18.1 “UART Baud Rate Generator”
• 18.2 “Transmitting in 8-bit Data Mode”
• 18.3 “Transmitting in 9-bit Data Mode”
• 18.4 “Break and Sync Transmit Sequence”
• 18.5 “Receiving in 8-bit or 9-bit Data Mode”
• 18.6 “Flow Control Using UxCTS and UxRTS Pins”
• 18.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 19-2).
Removed Equation 19-1: ADC Conversion Clock Period and Figure 19-2:
ADC Transfer Function (10-Bit Example).
Added ADC1 Module Block Diagram for dsPIC33FJ16MC304 and
dsPIC33FJ32MC204 Devices (Figure 20-1) and ADC1 Module Block
Diagram FOR dsPIC33FJ32MC202 Devices (Figure 20-2).
Added Note 2 to Figure 20-3: ADC Conversion Clock Period Block Diagram.
Updated ADC Conversion Clock Select bits in the AD1CON3 register from
ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been
updated throughout this data sheet (Register 20-3).
Added device-specific information to Note 1 in the ADC1 Input Scan Select
Register Low (see Register 20-6), and updated the default bit value for bits
12-10 (CSS12-CSS10) from U-0 to R/W-0.
Added device-specific information to Note 1 in the ADC1 Port Configuration
Register Low (see Register 20-7), and updated the default bit value for bits
12-10 (PCFG12-PCFG10) from U-0 to R/W-0.
2
2
C Interrupts”
C Module Addresses”
Update Description
© 2011 Microchip Technology Inc.
2
C Block Diagram)
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