DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 210
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
- Current page: 210 of 320
- Download datasheet (5Mb)
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
REGISTER 20-6:
REGISTER 20-7:
DS70283H-page 210
,2
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8-0
Note 1:
Note 1: On devices without 9 analog inputs, all AD1CSSL bits can be selected by the user application. However,
PCFG7
R/W-0
R/W-0
CSS7
U-0
U-0
—
—
2:
3:
2: CSSx = ANx, where x = 0 through 8.
On devices without 9 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are
ignored on ports without a corresponding input on device.
PCFGx = ANx, where x = 0 through 8.
The PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx Register.
In this case, all port pins multiplexed with ANx will be in Digital mode.
inputs selected for scan without a corresponding input on device converts V
Unimplemented: Read as ‘0’
CSS<8:0>: ADC Input Scan Selection bits
1 = Select ANx for input scan
0 = Skip ANx for input scan
Unimplemented: Read as ‘0’
PCFG<8:0>: ADC Port Configuration Control bits
1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AV
0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage
PCFG6
R/W-0
R/W-0
CSS6
U-0
U-0
—
—
AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW
AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
PCFG5
R/W-0
R/W-0
CSS5
U-0
U-0
—
—
PCFG4
R/W-0
R/W-0
CSS4
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
PCFG3
R/W-0
R/W-0
CSS3
U-0
U-0
—
—
PCFG2
R/W-0
R/W-0
CSS2
U-0
U-0
—
—
© 2011 Microchip Technology Inc.
REFL
(1,2)
x = Bit is unknown
x = Bit is unknown
.
PCFG1
R/W-0
R/W-0
CSS1
(1,2,3)
U-0
U-0
—
—
PCFG8
PCFG0
R/W-0
R/W-0
R/W-0
R/W-0
CSS8
CSS0
SS
bit 8
bit 0
bit 8
bit 0
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