DSPIC33FJ128MC202-E/SP Microchip Technology, DSPIC33FJ128MC202-E/SP Datasheet - Page 87
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DSPIC33FJ128MC202-E/SP
Manufacturer Part Number
DSPIC33FJ128MC202-E/SP
Description
16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC202-E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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FIGURE 6-2:
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Oscillator Clock
Device Status
Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active
SYSRST
FSCM
POR
BOR
V
DD
2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
until V
V
becomes stable.
period of time (T
at the appropriate level for full-speed operation. After the delay T
inactive, which in turn enables the selected oscillator to start generating clock cycles.
Table
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
is ready and the delay T
BOR
1
SYSTEM RESET TIMING
6-1. Refer to
DD
threshold and the delay T
crosses the V
2
T
PWRT
V
POR
POR
Section 9.0 “Oscillator Configuration”
) after a BOR. The delay T
POR
FSCM
threshold and the delay T
elapsed.
BOR
Vbor
V
BOR
has elapsed. The delay T
T
PWRT
T
3
BOR
Reset
Time
PWRT
ensures that the system power supplies have stabilized
POR
T
OSCD
has elapsed.
for more information.
BOR
PWRT
T
OST
ensures the voltage regulator output
4
has elapsed, the SYSRST becomes
T
LOCK
DS70291E-page 87
5
DD
6
Run
crosses the
T
FSCM
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