DSPIC33FJ128MC202-E/SP Microchip Technology, DSPIC33FJ128MC202-E/SP Datasheet - Page 26
![16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ128MC202-E/SP
Manufacturer Part Number
DSPIC33FJ128MC202-E/SP
Description
16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC202-E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
3.3
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions
instructions and have been designed for optimal
real-time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
DS70291E-page 26
DSP Engine Overview
operate
seamlessly
with
all
other
3.4
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 supports 16/16
and 32/16 divide operations, both fractional and inte-
ger. All divide instructions are iterative operations. They
must be executed within a REPEAT loop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
Special MCU Features
© 2011 Microchip Technology Inc.
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