DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 14

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F2010
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
• DIVF – 16/16 signed fractional divide
• DIV.sd – 32/16 signed divide
• DIV.ud – 32/16 unsigned divide
• DIV.sw – 16/16 signed divide
• DIV.uw – 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value, and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion, as shown in
target instruction {operand value + 1} times). The
REPEAT loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
TABLE 2-2:
DS70118J-page 14
DIVF
DIV.sd
DIV.ud
DIV.sw (or DIV.s)
DIV.uw (or DIV.u)
Note:
Divide Support
The Divide flow is interruptible; however,
the user needs to save the context as
appropriate.
Instruction
DIVIDE INSTRUCTIONS
Table 2-2
(REPEAT will execute the
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
2.4
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform inher-
ent
require no additional data. These instructions are ADD,
SUB, and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
• Fractional or integer DSP multiply (IF).
• Signed or unsigned DSP multiply (US).
• Conventional or convergent rounding (RND).
• Automatic saturation on/off for ACCA (SATA).
• Automatic saturation on/off for ACCB (SATB).
• Automatic saturation on/off for writes to data
• Accumulator Saturation mode selection (ACC-
A block diagram of the DSP engine is shown in
Figure
TABLE 2-1:
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY.N
MSC
memory (SATDW).
SAT).
Note:
Instruction
accumulator-to-accumulator
2-2.
DSP Engine
Function
For CORCON layout, see
DSP INSTRUCTION
SUMMARY
No change in A
A = A + (x – y)
A = A + (x • y)
A = A – x • y
Operation
A = (x – y)
Algebraic
A = A + x
A = – x • y
A = x • y
© 2011 Microchip Technology Inc.
A = 0
2
2
2
operations,
Table
ACC WB?
Yes
Yes
Yes
Yes
No
No
No
No
No
3-3.
which