CY8C3665AXI-016 Cypress Semiconductor Corp, CY8C3665AXI-016 Datasheet - Page 46
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CY8C3665AXI-016
Manufacturer Part Number
CY8C3665AXI-016
Description
CY8C3665AXI-016
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C36xxr
Specifications of CY8C3665AXI-016
Core Processor
8051
Core Size
8-Bit
Speed
67MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Peripherals
CapSense, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
CY8C36
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
1KB
Ram Memory Size
4KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C3665AXI-016
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY8C3665AXI-016T
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C36
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
Document Number: 001-53413 Rev. *L
Fixed Function DRQs
Counters
Timer
Clocks
Global
Fixed Function IRQs
Figure 7-14
IO Port
Pins
CAN
UDB Array
EMIF
shows the structure of the IDMUX
I2C
Interrupt and DMA Processing in IDMUX
Digital System Routing I/F
Digital System Routing I/F
IRQs
DRQs
UDB ARRAY
Del-Sig
Controller
Interrupt
Detect
Detect
Edge
Edge
SC/CT
Blocks
Controller
DMA
DACs
0
1
2
0
1
2
3
DMA termout (IRQs)
IO Port
Pins
Comparators
Controller
Controller
Interrupt
DMA
Clocks
Global
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see
from pins are synchronized as this is required if the CPU
interacts with the signal or any signal derived from it.
Asynchronous inputs have rare uses. An example of this is a
feed through of combinational PLD logic from input pins to output
pins.
Figure 7-15. I/O Pin Synchronization Routing
Figure 7-16. I/O Pin Output Connectivity
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
DO
DI
PIN 0
DO
8 IO Data Output Connections from the
UDB Array Digital System Interface
PIN1
DO
PIN2
DO
PSoC
Figure 6-1
PIN3
DO
Port i
®
PIN4
on page 26). Normally all inputs
DO
3: CY8C36 Family
PIN5
DO
Data Sheet
PIN6
DO
Page 46 of 126
PIN7
DO