CY8C3665AXI-016 Cypress Semiconductor Corp, CY8C3665AXI-016 Datasheet - Page 16
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CY8C3665AXI-016
Manufacturer Part Number
CY8C3665AXI-016
Description
CY8C3665AXI-016
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C36xxr
Specifications of CY8C3665AXI-016
Core Processor
8051
Core Size
8-Bit
Speed
67MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Peripherals
CapSense, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
CY8C36
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
1KB
Ram Memory Size
4KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C3665AXI-016
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY8C3665AXI-016T
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
4.4.2 DMA Features
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in
satisfied their requirements.
4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
Document Number: 001-53413 Rev. *L
24 DMA channels
Each channel has one or more transaction descriptors (TD) to
configure channel behavior. Up to 128 total TDs can be defined
TDs can be dynamically updated
Eight levels of priority per channel
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64 KB
TDs may be nested and/or chained for complex transactions
ADDR 16/32
Table 4-7
READY
WRITE
DATA
CLK
after the CPU and DMA priority levels 0 and 1 have
ADDRESS Phase
Basic DMA Read Transfer without wait states
A
DATA Phase
B
Figure 4-1. DMA Timing Diagram
DATA (A)
ADDR 16/32
Table 4-7. Priority Levels
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles shown in
Figure
to the Technical Reference Manual.
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.4.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
READY
WRITE
DATA
Priority Level
CLK
4-1. For more description on other transfer modes, refer
0
1
2
3
4
5
6
7
ADDRESS Phase
PSoC
Basic DMA Write Transfer without wait states
A
% Bus Bandwidth
®
3: CY8C36 Family
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
DATA Phase
DATA (A)
Data Sheet
B
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