CY8C3665AXI-016 Cypress Semiconductor Corp, CY8C3665AXI-016 Datasheet - Page 109

CY8C3665AXI-016

CY8C3665AXI-016

Manufacturer Part Number
CY8C3665AXI-016
Description
CY8C3665AXI-016
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C36xxr
Datasheets

Specifications of CY8C3665AXI-016

Core Processor
8051
Core Size
8-Bit
Speed
67MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Peripherals
CapSense, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
CY8C36
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
1KB
Ram Memory Size
4KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C3665AXI-016
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY8C3665AXI-016T
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
11.8.5 SWD Interface
Table 11-72. SWD Interface AC Specifications
11.8.6 SWV Interface
Table 11-73. SWV Interface AC Specifications
Document Number: 001-53413 Rev. *L
f_SWDCK
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T_SWDI_hold
T_SWDO_valid SWDCK high to SWDIO output
T_SWDO_hold SWDIO output hold after SWDCK low
Notes
57. Based on device characterization (Not production tested).
58. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Parameter
Parameter
(PSoC 3 reading on SWDIO)
(PSoC 3 writing to SWDIO)
SWDCLK frequency
SWDIO input hold after SWDCK high
SWV mode SWV bit rate
SWDCK
SWDIO
SWDIO
Description
Description
T_SWDI_setup
Figure 11-67. SWD Interface Timing
[57]
[57]
T_SWDI_hold
3.3 V ≤ V
1.71 V ≤ V
1.71 V ≤ V
SWD over USBIO pins
T = 1/f_SWDCK max
T = 1/f_SWDCK max
T = 1/f_SWDCK max
DDD
DDD
DDD
Conditions
Conditions
≤ 5 V
< 3.3 V
< 3.3 V,
T_SWDO_valid
(1/f_SWDCK)
PSoC
Min
Min
T/4
T/4
T/4
®
T_SWDO_hold
3: CY8C36 Family
Typ
Typ
Data Sheet
5.5
14
Max
2T/5
7
Page 109 of 126
Max
[58]
[58]
33
[58]
Units
MHz
MHz
MHz
Units
Mbit

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