CY7C1474V25-200BGXI Cypress Semiconductor Corp, CY7C1474V25-200BGXI Datasheet - Page 22

• Manufacturer Part Number: CY7C1474V25-200BGXI
• Description: CY7C1474V25-200BGXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1474V25-200BGXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (1M x 72)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 209-FBGA
• Density: 72Mb
• Access Time (max): 3ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 20b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 8
• Supply Current: 450mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 209
• Word Size: 72b
• Number Of Words: 1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05290 Rev. *L
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
Power
CYC
CH
CL
CO
OEV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
16. Timing reference is 1.25 V when V
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
19. t
20. At any given voltage and temperature, t
21. This parameter is sampled and not 100% tested.
MAX
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
[18]
, t
CLZ
, t
EOLZ
, and t
V
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z
Clock to low Z
OE HIGH to output high Z
OE LOW to Output low Z
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
WE, BW
ADV/LD set-up before CLK rise
Chip select set-up
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE, BW
ADV/LD hold after CLK rise
Chip select hold after CLK rise
CC
(typical) to the first access read or write
EOHZ
x
x
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
set-up before CLK rise
hold after CLK rise
[16, 17]
DDQ
[19, 20, 21]
[19, 20, 21]
Description
= 2.5 V and 0.9 V when V
EOHZ
power
is less than t
[19, 20, 21]
is the time power needs to be supplied above V
[19, 20, 21]
EOLZ
and t
DDQ
CHZ
= 1.8 V.
is less than t
Min
4.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
CLZ
–250
to eliminate bus contention between SRAMs when sharing the same
Max
250
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
minimum initially, before a read or write operation can be
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
–200
Max
200
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
6.0
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
–
–
0
–167
CY7C1470V25
CY7C1472V25
CY7C1474V25
Max
167
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 22 of 31
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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