CY7C1470V33-167AXI Cypress Semiconductor Corp, CY7C1470V33-167AXI Datasheet - Page 23

• Manufacturer Part Number: CY7C1470V33-167AXI
• Description: CY7C1470V33-167AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V33-167AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05289 Rev. *M
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
Power
CYC
CH
CL
CO
OEV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
19. Timing reference is 1.5 V when V
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; t
22. t
23. At any voltage and temperature, t
24. This parameter is sampled and not 100% tested.
MAX
Parameter
initiated.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve high Z prior to low Z under the same system conditions.
CHZ
[21]
, t
CLZ
, t
EOLZ
, and t
V
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z
Clock to low Z
OE HIGH to output high Z
OE LOW to output low Z
Address setup before CLK rise
Data input setup before CLK rise
CEN setup before CLK rise
WE, BW
ADV/LD setup before CLK rise
Chip select setup
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE, BW
ADV/LD hold after CLK rise
Chip select hold after CLK rise
CC
EOHZ
(typical) to the first access read or write
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[19, 20]
x
x
setup before CLK rise
hold after CLK rise
DDQ
EOHZ
= 3.3 V and is 1.25 V when V
[22, 23, 24]
is less than t
[22, 23, 24]
Description
power
is the time power needs to be supplied above V
[22, 23, 24]
EOLZ
[22, 23, 24]
and t
CHZ
is less than t
DDQ
= 2.5 V.
CLZ
Min
to eliminate bus contention between SRAMs when sharing the same data
2.0
2.0
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
4.0
1.3
1
–
–
–
–
–
0
–250
Max
250
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
minimum initially, before a read or write operation can be
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
–200
Max
200
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
6.0
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
–
–
0
CY7C1470V33
CY7C1472V33
CY7C1474V33
–167
Max
167
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 23 of 33
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback