CY7C1470V33-167AXI Cypress Semiconductor Corp, CY7C1470V33-167AXI Datasheet - Page 11

• Manufacturer Part Number: CY7C1470V33-167AXI
• Description: CY7C1470V33-167AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V33-167AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Truth Table
The Truth Table for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows.
Notes
Document Number: 38-05289 Rev. *M
Deselect cycle
Continue deselect
cycle
Read cycle (begin
burst)
Read cycle (continue
burst)
NOP/dummy read
(begin burst)
Dummy read (continue
burst)
Write cycle (begin
burst)
Write cycle (continue
burst)
NOP/write abort (begin
burst)
Write abort (continue
burst)
Ignore clock edge
(stall)
Sleep mode
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = 0 signifies at least one byte write select is active, BWx = valid signifies
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ
that the desired byte write selects are asserted, see Write Cycle Description table for details.
inactive or when the device is deselected, and DQ
Operation
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
Address Used
[a:d]
. See Write Cycle Description table for details.
s
= data when OE is active.
CE
H
X
L
X
L
X
L
X
L
X
X
X
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
ADV/LD
H
H
H
H
H
L
L
L
L
L
X
X
WE
X
X
H
X
H
X
X
X
X
X
L
L
BW
H
H
X
X
X
X
X
X
X
X
L
L
x
[1, 2, 3, 4, 5, 6, 7]
OE
X
X
H
H
X
X
X
X
X
X
L
L
CEN
H
X
L
L
L
L
L
L
L
L
L
L
CLK
s
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
and DQP
X
CY7C1470V33
CY7C1472V33
CY7C1474V33
[a:d]
Data out (Q)
Data out (Q)
Data in (D)
Data in (D)
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
= tristate when OE is
DQ
–
Page 11 of 33
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