CY7C1470V33-167AXI Cypress Semiconductor Corp, CY7C1470V33-167AXI Datasheet - Page 17

• Manufacturer Part Number: CY7C1470V33-167AXI
• Description: CY7C1470V33-167AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V33-167AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document Number: 38-05289 Rev. *M
Revision number (31:29)
Device depth (28:24)
Architecture/memory
type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code
(11:1)
ID register presence
indicator (0)
Instruction
Bypass
ID
Boundary scan order - 165 FBGA
Boundary scan order - 209 FBGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
Note
15. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Instruction Field
Instruction
Register Name
[15]
Code
100
000
001
010
011
101
CY7C1470V33
00000110100
(2 M × 36)
001000
100100
01011
000
1
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Bit Size (× 36)
32
71
3
1
–
CY7C1472V33
00000110100
(4 M × 18)
001000
010100
01011
000
1
Bit Size (× 18)
CY7C1474V33
00000110100
(1 M × 72)
001000
110100
01011
Description
32
52
000
3
1
–
1
Describes the version number
Reserved for internal use
Defines memory type and
architecture
Defines width and density
Allows unique identification of
SRAM vendor
Indicates the presence of an ID
register
Description
Bit Size (× 72)
CY7C1470V33
CY7C1472V33
CY7C1474V33
110
32
3
1
–
Page 17 of 33
[+] Feedback