CY7C1470BV33-200BZCT Cypress Semiconductor Corp, CY7C1470BV33-200BZCT Datasheet - Page 7

• Manufacturer Part Number: CY7C1470BV33-200BZCT
• Description: CY7C1470BV33-200BZCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470BV33-200BZCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1. Pin Definitions
Document #: 001-15031 Rev. *C
A0
A1
A
BW
BW
BW
BW
BW
BW
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DQP
MODE
TDO
TDI
Pin Name
1
2
3
S
a
b
c
d
e
f
g
h
X
JTAG Serial Input
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
JTAG Serial
IO Type
Output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
IO-
IO-
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK.
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQ
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New
Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD
must be driven LOW to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to
control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs.
When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ
sequences, DQP
and DQP
is controlled by BW
Pulled LOW selects the linear burst order. MODE must not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
2
1
c
and CE
and CE
controls DQ
1
d
and CE
is controlled by BW
f
2
3
and DQP
to select or deselect the device.
to select or deselect the device.
[17:0]
c
3
a
and DQP
is controlled by BW
to select or deselect the device.
during the previous clock rise of the read cycle. The direction of the pins is
g
, DQP
f
, BW
h
g
c
is controlled by BW
a
, BW
controls DQ
–DQ
d
, DQP
d
d
controls DQ
are placed in a tri-state condition. The outputs are automat-
a
e
, DQP
Pin Description
a
is controlled by BW
controls DQ
g
and DQP
b
CY7C1472BV33, CY7C1474BV33
is controlled by BW
d
h
and DQP
.
g
a
, BW
and DQP
d
h
e
, BW
, DQP
controls DQ
a
e
, BW
controls DQ
b
f
, DQP
is controlled by BW
b
controls DQ
h
c
CY7C1470BV33
and DQP
is controlled by BW
e
and DQP
X
. During write
b
h
.
and DQP
f
, DQP
Page 7 of 30
e
, BW
b
c
g
,
f
,
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