CY7C1470BV33-167AXC Cypress Semiconductor Corp, CY7C1470BV33-167AXC Datasheet

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... Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle ...

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... Logic Block Diagram – CY7C1470BV33 (2M x 36) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Logic Block Diagram – CY7C1472BV33 (4M x 18) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Document #: 001-15031 Rev. *G CY7C1472BV33, CY7C1474BV33 ...

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... CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Document #: 001-15031 Rev. *G CY7C1472BV33, CY7C1474BV33 ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT E REGISTER 1 READ LOGIC Sleep Control CY7C1470BV33 ...

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... DQb DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1470BV33 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa ( DQa 63 DQa DDQ DQa 59 DQa DDQ Page [+] Feedback ...

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... DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A Document #: 001-15031 Rev. *G CY7C1472BV33, CY7C1474BV33 165-Ball FBGA ( 1.4 mm) CY7C1470BV33 ( CEN CLK TDO A TDI A0 TCK A TMS CY7C1472BV33 (4M x 18) ...

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... DDQ V CEN DDQ DDQ DDQ MODE TDI CY7C1470BV33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ V V DQf SS SS DQf V V DDQ DQf DQf DDQ NC NC ...

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... The direction of the pins is [17:0] –DQ are placed in a tri-state condition. The outputs are automat controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1470BV33 and DQP , BW controls DQ and DQP controls DQ and DQP , controls DQ and DQP . ...

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... ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition Asynchronous with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull-down. Document #: 001-15031 Rev. *G CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Pin Description Page [+] Feedback ...

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... Functional Overview The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are synchronous-pipelined Burst NoBL SRAMs designed specif- ically to eliminate wait states during read or write transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN) ...

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... Chip Enables ( and are ignored and the burst counter is incremented. The correct BW (BW for CY7C1470BV33, BW a,b,c,d and BW for CY7C1474BV33) inputs must be driven a,b,c,d,e,f,g,h in each cycle of the burst write to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “ ...

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... Table 3. Truth Table The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Operation Address Used Deselect Cycle None Continue None Deselect Cycle Read Cycle External (Begin Burst) Read Cycle Next (Continue Burst) NOP/Dummy Read External (Begin Burst) Dummy Read Next (Continue Burst) ...

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... Table 4. Partial Write Cycle Description The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Function (CY7C1470BV33) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – (DQ ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...

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... SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1470BV33 Page [+] Feedback ...

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... BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Figure 4. TAP Timing TDIS t TDIH t TDOX DON’ UNDEFINED CY7C1470BV33 TDOV Page [+] Feedback ...

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... Capture Hold after Clock Rise CH Notes 9. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 10. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-15031 Rev. *G CY7C1472BV33, CY7C1474BV33 Description / ns CY7C1470BV33 Min Max Unit MHz ...

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... OL DDQ 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1470BV33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...

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... Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. CY7C1470BV33 Description Describes the version number Reserved for internal use ...

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... M10 58 A8 L10 59 B8 K11 60 A7 165-Ball ID Bit # 165-Ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1470BV33 Bit # 165-Ball Bit # 165-Ball ID 40 B10 ...

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... W6 71 J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1470BV33 Bit # 209-Ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 C8 104 ...

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... SS Input = V DD ≤ V Output Disabled I DDQ, /2). Undershoot: V (AC)> –2V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1470BV33 Test Con- Description Typ Max* ditions Logical 25°C 361 394 Single Bit Upsets Logical Multi 25°C 0 0.01 Bit Upsets Single Event 85° ...

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... MHz DD ≤ 0. − 0.3V > DDQ 5.0-ns cycle, 200 MHz = f = 1/t MAX CYC 6.0-ns cycle, 167 MHz Max Device Deselected, All speed grades DD ≥ V ≤ CY7C1470BV33 Min Max Unit 500 mA 500 mA 450 mA 245 mA 245 mA 245 mA 120 mA 245 mA 245 mA 245 mA 135 mA Page [+] Feedback ...

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... EIA/JESD51 317Ω 3.3V V OUTPUT DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1470BV33 100 TQFP 165 FBGA 209 FBGA Max Max Max 165 FBGA 209 FBGA Package Package Package 24 ...

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... DD “AC Test Loads and Waveforms” on page and t is less than t to eliminate bus contention between SRAMs when sharing the same data EOLZ CHZ CLZ CY7C1470BV33 = 2.5V. Test conditions shown in DDQ –200 –167 Unit Min Max Min ...

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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1470BV33 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) ...

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... D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE [24, 25] Figure 7. ZZ Mode Timing High-Z DON’T CARE “Truth Table” on page 11 for all possible signal conditions to deselect the device. CY7C1470BV33 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) ...

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... Table 10. Ordering Information Speed Package (MHz) Ordering Code Diagram 167 CY7C1470BV33-167AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1470BV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-free CY7C1470BV33-167AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1472BV33-167AXI CY7C1470BV33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( ...

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... Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) Document #: 001-15031 Rev. *G CY7C1472BV33, CY7C1474BV33 Figure 9. 165-Ball FBGA ( 1.4 mm) CY7C1470BV33 51-85050 *C 51-85165 *B Page [+] Feedback ...

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... Package Diagrams (continued) Document #: 001-15031 Rev. *G CY7C1472BV33, CY7C1474BV33 Figure 10. 209-Ball FBGA ( 1.76 mm) CY7C1470BV33 51-85167 *A Page [+] Feedback ...

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... Document History Page Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72 Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 001-15031 Orig. of Revision ECN Change ** 1032642 VKN/KKVTMP *A 1897447 VKN/AESA *B 2082487 VKN *C 2159486 VKN/PYRS *D 2755901 VKN *E 2903057 VKN *F 2953769 YHB *G 3052861 NJY Document #: 001-15031 Rev. *G ...

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... NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1472BV33, CY7C1474BV33 cypress.com/go/plc Revised October 8, 2010 CY7C1470BV33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...