CY7C1470BV33-200BZCT Cypress Semiconductor Corp, CY7C1470BV33-200BZCT Datasheet - Page 22

• Manufacturer Part Number: CY7C1470BV33-200BZCT
• Description: CY7C1470BV33-200BZCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470BV33-200BZCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range. Timing reference is 1.5V when V
(a) of
Notes
Document #: 001-15031 Rev. *C
16. This part has an internal voltage regulator; t
17. t
18. At any voltage and temperature, t
19. This parameter is sampled and not 100% tested.
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Power
CYC
CH
CL
CO
OEV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
MAX
from steady-state voltage.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
Parameter
CHZ
“AC Test Loads and Waveforms” on page 21
[16]
, t
CLZ
, t
EOLZ
, and t
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Address Setup Before CLK Rise
Data Input Setup Before CLK Rise
CEN Setup Before CLK Rise
WE, BW
ADV/LD Setup Before CLK Rise
Chip Select Setup
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
EOHZ
CC
(typical) to the First Access Read or Write
are specified with AC test conditions shown in (b) of
x
x
EOHZ
Setup Before CLK Rise
Hold After CLK Rise
is less than t
[17, 18, 19]
[17, 18, 19]
Description
power
is the time power is supplied above V
EOLZ
[17, 18, 19]
[17, 18, 19]
and t
unless otherwise noted.
CHZ
is less than t
DDQ
CLZ
= 3.3V and is 1.25V when V
“AC Test Loads and Waveforms” on page
to eliminate bus contention between SRAMs when sharing the same data
Min
4.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
DD
–250
minimum initially, before a read or write operation can be initiated.
CY7C1472BV33, CY7C1474BV33
Max
250
3.0
3.0
3.0
3.0
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
–200
DDQ
Max
200
3.0
3.0
3.0
3.0
21. Transition is measured ±200 mV
= 2.5V. Test conditions shown in
Min
CY7C1470BV33
6.0
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
–167
Max
167
3.4
3.4
3.4
3.4
Page 22 of 30
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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