CY7C1470BV33-167AXCT Cypress Semiconductor Corp, CY7C1470BV33-167AXCT Datasheet - Page 9

• Manufacturer Part Number: CY7C1470BV33-167AXCT
• Description: CY7C1470BV33-167AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470BV33-167AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
CY7C1472BV25,
CY7C1474BV25) (or a subset for Byte Write operations, see
Partial Write Cycle Description on page 11
latched into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
BW
CY7C1470BV25,
provides Byte Write capability that is described in
Cycle Description on page
selected BW input selectively writes to only the desired bytes.
Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte Write capability
has been included to greatly simplify read, modify, or write
sequences, which can be reduced to simple Byte Write
operations.
Because
CY7C1474BV25 are common IO devices, data must not be
driven into the device while the outputs are active. OE can be
deasserted HIGH before presenting data to the DQ and DQP
(DQ
CY7C1472BV25,
CY7C1474BV25) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQ
CY7C1470BV25, DQ
DQ
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in
on page
ZZ Mode Electrical Characteristics
Document Number: 001-15032 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d
a,b,c,d
a,b,c,d
Parameter
8. When ADV/LD is driven HIGH on the subsequent
/DQP
/DQP
for CY7C1470BV25, BW
the
/DQP
a,b,c,d
a,b,c,d
CY7C1470BV25,
for
a,b,c,d,e,f,g,h
CY7C1472BV25,
and
for CY7C1470BV25, DQ
for CY7C1470BV25, DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
a,b
DQ
/DQP
CY7C1474BV25)
a,b,c,d,e,f,g,h
DQ
11. Asserting the WE input with the
a,b,c,d,e,f,g,h
a,b
for
a,b
Description
for CY7C1472BV25, and
/DQP
for CY7C1472BV25, and
CY7C1472BV25,
CY7C1474BV25)
and
Single Write Accesses
/DQP
a,b,c,d,e,f,g,h
a,b,c,d
for details) inputs is
CY7C1474BV25
a,b,c,d,e,f,g,h
signals.
a,b
a,b
/DQP
Partial Write
/DQP
/DQP
a,b,c,d
a,b
a,b
The
and
are
for
for
for
for
for
ZZ  V
ZZV
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
clock rise, the Chip Enables (CE
are ignored and the burst counter is incremented. The correct
BW (BW
and BW
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or V
DD
DD
 0.2 V
 0.2 V
Address
Test Conditions
Address
A1, A0
A1, A0
First
First
3
00
01
10
11
00
01
10
a,b,c,d,e,f,g,h
11
, must remain inactive for the duration of t
a,b,c,d
CY7C1472BV25, CY7C1474BV25
for CY7C1470BV25, BW
for CY7C1474BV25) inputs must be driven
Address
Address
Second
Second
A1, A0
A1, A0
01
00
11
10
01
10
11
00
1
DD
, CE
2t
)
Min
CYC
CY7C1470BV25
Address
Address
2
–
–
–
0
, and CE
A1, A0
A1, A0
Third
Third
a,b
10
11
00
01
10
00
01
11
for CY7C1472BV25,
2t
2t
Max
3
120
) and WE inputs
CYC
CYC
–
–
ZZREC
Page 9 of 28
Address
Address
Fourth
Fourth
A1, A0
A1, A0
00
01
10
10
01
00
11
11
after the
1
Unit
mA
, CE
ns
ns
ns
ns
2
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