CY7C1371D-100AXCT Cypress Semiconductor Corp, CY7C1371D-100AXCT Datasheet - Page 11

• Manufacturer Part Number: CY7C1371D-100AXCT
• Description: CY7C1371D-100AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1371D-100AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

enable input (WE) with the selected byte write select input
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remains unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included to
greatly simplify read/modify/write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1371D/CY7C1373D is a common IO device,
data must not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP
the output drivers. As a safety precaution, DQs and DQP
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW to load the initial address,
as described in the
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE
burst counter is incremented. The correct BW
driven in each cycle of the burst write, to write the correct bytes
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
ZZ Mode Electrical Characteristics
Document Number: 38-05556 Rev. *I
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
1
, CE
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
2
, and CE
Single Write Accesses
3
) and WE inputs are ignored and the
Description
X
inputs. Doing so tri-states
section above. When
X
inputs must be
X
are
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
Test Conditions
Address
Address
A1: A0
A1: A0
DD
DD
First
First
00
01
10
00
01
10
11
11
3
– 0.2 V
, must remain inactive for the duration of t
– 0.2 V
Address
Address
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
2t
Min
CYC
–
–
–
0
DD
Address
Address
A1: A0
A1: A0
Third
Third
)
10
00
01
10
00
01
11
11
2t
2t
Max
80
CYC
CYC
–
–
CY7C1371D
CY7C1373D
ZZREC
Address
Address
Page 11 of 33
Fourth
A1: A0
Fourth
A1: A0
Unit
mA
ns
ns
ns
ns
10
01
00
00
01
10
11
11
after the
1
, CE
2
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