CY7C1363C-133AJXI Cypress Semiconductor Corp, CY7C1363C-133AJXI Datasheet - Page 26

• Manufacturer Part Number: CY7C1363C-133AJXI
• Description: CY7C1363C-133AJXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1363C-133AJXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Diagrams
Notes
Document Number: 38-05541 Rev. *J
28. On this diagram, when CE is LOW: CE
29. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
30. GW is HIGH.
Data Out (Q)
Data In (D)
BWE, BW
ADDRESS
ADSC
ADSP
ADV
CLK
OE
CE
X
A1
High-Z
t ADS
Back-to-Back READs
t CES
t AS
Q(A1)
(continued)
A2
t ADH
t CEH
t
t AH
CH
t CYC
t
CL
1
Q(A2)
is LOW, CE
t
OEHZ
Figure 8. Read/Write Cycle Timing
A3
2
is HIGH and CE
Single WRITE
t
t DS
WES
D(A3)
t DH
t
WEH
3
is LOW. When CE is HIGH: CE
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
UNDEFINED
[28, 29, 30]
Q(A4+1)
BURST READ
1
is HIGH or CE
Q(A4+2)
CY7C1361C/CY7C1363C
2
is LOW or CE
Q(A4+3)
3
D(A5)
is HIGH.
Back-to-Back
A5
WRITEs
Page 26 of 34
D(A6)
A6
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