CY7C1363C-133AJXI Cypress Semiconductor Corp, CY7C1363C-133AJXI Datasheet - Page 25

• Manufacturer Part Number: CY7C1363C-133AJXI
• Description: CY7C1363C-133AJXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1363C-133AJXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Diagrams
Notes
Document Number: 38-05541 Rev. *J
26. On this diagram, when CE is LOW: CE
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data in (D)
ADDRESS
BWE,
ADSC
ADSP
GW
ADV
CE
CLK
BW
OE
X
BURST READ
High-Z
t ADS
t CES
t AS
(continued)
A1
t ADH
t
t AH
t CEH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t
Single WRITE
CL
t
DS
D(A1)
1
t ADH
t
DH
is LOW, CE
A2
2
Figure 7. Write Cycle Timing
is HIGH and CE
D(A2)
DON’T CARE
D(A2 + 1)
t
WES
3
BURST WRITE
is LOW. When CE is HIGH: CE
t
WEH
D(A2 + 1)
UNDEFINED
ADV suspends burst
X
D(A2 + 2)
LOW.
[26, 27]
ADSC extends burst
D(A2 + 3)
1
is HIGH or CE
t ADS
CY7C1361C/CY7C1363C
A3
D(A3)
t ADH
2
t ADVS
is LOW or CE
Extended BURST WRITE
t WES
D(A3 + 1)
t ADVH
t WEH
D(A3 + 2)
3
is HIGH.
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