CY7C1339G-133AXCT Cypress Semiconductor Corp, CY7C1339G-133AXCT Datasheet - Page 5

• Manufacturer Part Number: CY7C1339G-133AXCT
• Description: CY7C1339G-133AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1339G-133AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
device).
The CY7C1339G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
Document Number: 38-05520 Rev. *I
OE
ADV
ADSP
ADSC
ZZ
DQs
V
V
V
V
MODE
NC,NC/9M,
NC/18M.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
DD
SS
DDQ
SSQ
Name
asynchronous
asynchronous
Power supply Power supply inputs to the core of the device.
synchronous
synchronous
synchronous
synchronous
I/O ground
I/O power
Ground
supply
Input-
Input-
Input-
Input-
Input-
Input-
static
I/O-
I/O
–
(continued)
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The direction
of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs are placed in a tri-state condition.
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode pin has an internal pull-up.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
CO
) is 2.6 ns (250-MHz
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
1
is deasserted HIGH.
Description
[A:D]
) inputs. A global write
1
, CE
CY7C1339G
2
, CE
DD
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