CY7C027-20AXCT Cypress Semiconductor Corp, CY7C027-20AXCT Datasheet - Page 7

• Manufacturer Part Number: CY7C027-20AXCT
• Description: CY7C027-20AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C027-20AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 512K (32K x 16)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Document #: 38-06042 Rev. *F
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
ABE
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
16. At any given temperature and voltage condition for any given device, t
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to
20. Test conditions used are Load 1.
Read Cycle
Write Cycle
Busy Timing
Parameter
[18]
[18]
[15]
and 30 pF load capacitance.
[15]
[15]
[15]
[21]
[19]
[19]
[16, 17, 18]
[16, 17, 18]
[16, 17, 18]
[16, 17, 18]
[17, 18]
[17, 18]
[20]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
Data Setup to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
Description
Over the Operating Range
HZCE
is less than t
[14]
Min
12
12
10
10
10
10
11
3
3
3
0
0
0
0
3
5
0
LZCE
-12
and t
[1]
Max
12
12
10
10
12
12
10
25
20
12
12
12
12
12
HZOE
8
Figure
is less than t
11.
CY7C027/028
CY7C037/038
Min
15
15
12
12
12
10
13
3
3
3
0
0
0
0
3
5
0
LZOE
-15
.
SCE
Max
15
15
10
10
10
15
15
10
30
25
15
15
15
15
15
time.
Min
20
20
15
15
15
15
15
3
3
3
0
0
0
0
3
5
0
CY7C027/028
CY7C037/038
-20
Max
20
20
12
12
12
20
20
12
45
30
20
20
20
17
20
Page 7 of 19
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OI
/I
OH
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