CY7C026A-15AXI Cypress Semiconductor Corp, CY7C026A-15AXI Datasheet - Page 4

• Manufacturer Part Number: CY7C026A-15AXI
• Description: CY7C026A-15AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C026A-15AXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 256K (16K x 16)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Architecture
The CY7C026A consist of an array of 16K words of 16 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle simulta-
neous writes/reads to the same location, a BUSY pin is provided
on each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control pins
are used for allocating shared resources. With the M/S pin, the
devices can function as a master (BUSY pins are outputs) or as
a slave (BUSY pins are inputs). The devices also have an
automatic power down feature controlled by CE. Each port is
provided with its own Output Enable control (OE), which allows
data to be read from the device.
Functional Description
The CY7C026A is a low power CMOS 16K x 16 dual-port static
RAM. Various arbitration schemes are included on the devices
to handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The device can be utilized as standalone 16-bit
dual-port static RAM or multiple devices can be combined to
function as a 32-bit or wider master/slave dual-port static RAM.
An M/S pin is provided for implementing 32-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
Document #: 38-06046 Rev. *F
CE
R/W
OE
A
I/O
SEM
UB
LB
INT
BUSY
M/S
V
GND
NC
0L
CC
L
L
0L
L
L
–A
L
L
L
–I/O
L
13L
Left Port
15L
CE
R/W
OE
A
I/O
SEM
UB
LB
INT
BUSY
0R
R
R
0R
R
R
R
–A
R
R
–I/O
R
13R
Right Port
15R
Chip enable
Read/Write enable
Output enable
Address
Data bus input/output
Semaphore enable
Upper byte select (I/O
Lower byte select (I/O
Interrupt flag
Busy flag
Master or slave select
Power
Ground
No connect
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by the chip enable pin.
The CY7C026A is available in 100-pin thin quad plastic flatpack
(TQFP) packages.
Write Operation
Data must be set up for a duration of t
of R/W to either the R/W pin (see
Figure
summarized in
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox for
the right port and the second highest memory location (3FFE) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
8
0
7). Required inputs for non-contention operations are
–I/O
–I/O
15
7
for x16 devices)
for x16 devices)
Table
Description
1.
ACE
after CE or t
Figure
SD
before the rising edge
6) or the CE pin (see
CY7C026A
DOE
Page 4 of 20
after OE is
DDD
after
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